1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip USB2.0 PHY with Naneng IP block driver 4 * 5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <dm/lists.h> 11 #include <generic-phy.h> 12 #include <syscon.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <reset-uclass.h> 16 17 #define U2PHY_BIT_WRITEABLE_SHIFT 16 18 19 struct rockchip_usb2phy; 20 21 enum power_supply_type { 22 POWER_SUPPLY_TYPE_UNKNOWN = 0, 23 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 24 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 25 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 26 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 27 }; 28 29 enum rockchip_usb2phy_port_id { 30 USB2PHY_PORT_OTG, 31 USB2PHY_PORT_HOST, 32 USB2PHY_NUM_PORTS, 33 }; 34 35 struct usb2phy_reg { 36 u32 offset; 37 u32 bitend; 38 u32 bitstart; 39 u32 disable; 40 u32 enable; 41 }; 42 43 /** 44 * struct rockchip_chg_det_reg: usb charger detect registers 45 * @chg_valid: charge valid signal. 46 * @phy_connect: PHY start handshake signal. 47 * @chg_en: charge detector enable signal. 48 * @chg_rst: charge detector reset signal, active high. 49 */ 50 struct rockchip_chg_det_reg { 51 struct usb2phy_reg chg_valid; 52 struct usb2phy_reg phy_connect; 53 struct usb2phy_reg chg_en; 54 struct usb2phy_reg chg_rst; 55 }; 56 57 /** 58 * struct rockchip_usb2phy_port_cfg: usb phy port configuration. 59 * @bypass_otgsuspendm: otg-suspendm bypass control register. 60 * 0: iddig; 1: grf. 61 * @bvalidfall_det_en: vbus valid fall detection enable register. 62 * @bvalidfall_det_st: vbus valid fall detection status register. 63 * @bvalidfall_det_clr: vbus valid fall detection clear register. 64 * @bvalidrise_det_en: vbus valid rise detection enable register. 65 * @bvalidrise_det_st: vbus valid rise detection status register. 66 * @bvalidrise_det_clr: vbus valid rise detection clear register. 67 * @disconfall_det_en: host connect detection enable register. 68 * @disconfall_det_st: host connect detection status register. 69 * @disconfall_det_clr: host connect detection clear register. 70 * @disconrise_det_en: host disconnect detection enable register. 71 * @disconrise_det_st: host disconnect detection status register. 72 * @disconrise_det_clr: host disconnect detection clear register. 73 * @idfall_det_en: id fall detection enable register. 74 * @idfall_det_st: id fall detection state register. 75 * @idfall_det_clr: id fall detection clear register. 76 * @idpullup: id pin pullup or pulldown control register. 77 * @idrise_det_en: id rise detection enable register. 78 * @idrise_det_st: id rise detection state register. 79 * @idrise_det_clr: id rise detection clear register. 80 * @ls_det_en: linestate detection enable register. 81 * @ls_det_st: linestate detection state register. 82 * @ls_det_clr: linestate detection clear register. 83 * @phy_sus: phy suspend register. 84 * @utmi_bvalid: utmi vbus bvalid status register. 85 * @utmi_iddig: otg port id pin status register. 86 * @utmi_hostdet: utmi host disconnect status register. 87 */ 88 struct rockchip_usb2phy_port_cfg { 89 struct usb2phy_reg bypass_otgsuspendm; 90 struct usb2phy_reg bvalidfall_det_en; 91 struct usb2phy_reg bvalidfall_det_st; 92 struct usb2phy_reg bvalidfall_det_clr; 93 struct usb2phy_reg bvalidrise_det_en; 94 struct usb2phy_reg bvalidrise_det_st; 95 struct usb2phy_reg bvalidrise_det_clr; 96 struct usb2phy_reg disconfall_det_en; 97 struct usb2phy_reg disconfall_det_st; 98 struct usb2phy_reg disconfall_det_clr; 99 struct usb2phy_reg disconrise_det_en; 100 struct usb2phy_reg disconrise_det_st; 101 struct usb2phy_reg disconrise_det_clr; 102 struct usb2phy_reg idfall_det_en; 103 struct usb2phy_reg idfall_det_st; 104 struct usb2phy_reg idfall_det_clr; 105 struct usb2phy_reg idpullup; 106 struct usb2phy_reg idrise_det_en; 107 struct usb2phy_reg idrise_det_st; 108 struct usb2phy_reg idrise_det_clr; 109 struct usb2phy_reg ls_det_en; 110 struct usb2phy_reg ls_det_st; 111 struct usb2phy_reg ls_det_clr; 112 struct usb2phy_reg phy_sus; 113 struct usb2phy_reg utmi_bvalid; 114 struct usb2phy_reg utmi_iddig; 115 struct usb2phy_reg utmi_hostdet; 116 }; 117 118 /** 119 * struct rockchip_usb2phy_cfg: usb phy configuration. 120 * @reg: the address offset of grf for usb-phy config. 121 * @num_ports: specify how many ports that the phy has. 122 * @phy_tuning: phy default parameters tuning. 123 * @clkout_ctl: keep on/turn off output clk of phy. 124 * @port_cfgs: ports register configuration, assigned by driver data. 125 * @chg_det: charger detection registers. 126 * @last: indicate the last one. 127 */ 128 struct rockchip_usb2phy_cfg { 129 unsigned int reg; 130 unsigned int num_ports; 131 int (*phy_tuning)(struct rockchip_usb2phy *rphy); 132 struct usb2phy_reg clkout_ctl; 133 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 134 const struct rockchip_chg_det_reg chg_det; 135 bool last; 136 }; 137 138 /** 139 * struct rockchip_usb2phy: usb2.0 phy driver data. 140 * @grf: General Register Files register base. 141 * @reset: power reset signal for phy. 142 * @phy_cfg: phy register configuration, assigned by driver data. 143 */ 144 struct rockchip_usb2phy { 145 void __iomem *grf; 146 struct reset_ctl *reset; 147 const struct rockchip_usb2phy_cfg *phy_cfg; 148 }; 149 150 static inline int property_enable(void __iomem *base, 151 const struct usb2phy_reg *reg, bool en) 152 { 153 u32 val, mask, tmp; 154 155 tmp = en ? reg->enable : reg->disable; 156 mask = GENMASK(reg->bitend, reg->bitstart); 157 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 158 159 writel(val, base + reg->offset); 160 161 return 0; 162 } 163 164 static inline bool property_enabled(void __iomem *base, 165 const struct usb2phy_reg *reg) 166 { 167 u32 tmp, orig; 168 u32 mask = GENMASK(reg->bitend, reg->bitstart); 169 170 orig = readl(base + reg->offset); 171 172 tmp = (orig & mask) >> reg->bitstart; 173 174 return tmp == reg->enable; 175 } 176 177 static const char *chg_to_string(enum power_supply_type chg_type) 178 { 179 switch (chg_type) { 180 case POWER_SUPPLY_TYPE_USB: 181 return "USB_SDP_CHARGER"; 182 case POWER_SUPPLY_TYPE_USB_DCP: 183 return "USB_DCP_CHARGER"; 184 case POWER_SUPPLY_TYPE_USB_CDP: 185 return "USB_CDP_CHARGER"; 186 case POWER_SUPPLY_TYPE_USB_FLOATING: 187 return "USB_FLOATING_CHARGER"; 188 default: 189 return "INVALID_CHARGER"; 190 } 191 } 192 193 int rockchip_chg_get_type(void) 194 { 195 const struct rockchip_usb2phy_port_cfg *port_cfg; 196 enum power_supply_type chg_type; 197 struct rockchip_usb2phy *rphy; 198 struct udevice *udev; 199 bool chg_valid, phy_connect; 200 int cnt; 201 int ret; 202 203 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 204 if (ret == -ENODEV) { 205 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 206 return ret; 207 } 208 209 rphy = dev_get_priv(udev); 210 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 211 212 /* Check USB-Vbus status first */ 213 if (!property_enabled(rphy->grf, &port_cfg->utmi_bvalid)) { 214 pr_info("%s: no charger found\n", __func__); 215 return POWER_SUPPLY_TYPE_UNKNOWN; 216 } 217 218 reset_assert(rphy->reset); 219 220 /* CHG_RST is set to 1'b0 to start charge detection */ 221 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true); 222 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false); 223 224 for (cnt = 0; cnt < 12; cnt++) { 225 mdelay(100); 226 227 chg_valid = property_enabled(rphy->grf, 228 &rphy->phy_cfg->chg_det.chg_valid); 229 phy_connect = 230 property_enabled(rphy->grf, 231 &rphy->phy_cfg->chg_det.phy_connect); 232 chg_type = (chg_valid << 1) | phy_connect; 233 234 if (chg_type) 235 goto compeleted; 236 } 237 238 compeleted: 239 debug("charger = %s\n", chg_to_string(chg_type)); 240 241 mdelay(1); 242 reset_deassert(rphy->reset); 243 /* disable the chg detection module */ 244 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true); 245 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false); 246 247 return chg_type; 248 } 249 250 int rockchip_u2phy_vbus_detect(void) 251 { 252 int chg_type; 253 254 chg_type = rockchip_chg_get_type(); 255 256 return (chg_type == POWER_SUPPLY_TYPE_USB || 257 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 258 } 259 260 static int rockchip_usb2phy_init(struct phy *phy) 261 { 262 struct udevice *parent = phy->dev->parent; 263 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 264 const struct rockchip_usb2phy_port_cfg *port_cfg; 265 266 if (phy->id == USB2PHY_PORT_OTG) { 267 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 268 } else if (phy->id == USB2PHY_PORT_HOST) { 269 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 270 } else { 271 dev_err(phy->dev, "phy id %lu not support", phy->id); 272 return -EINVAL; 273 } 274 275 property_enable(rphy->grf, &port_cfg->phy_sus, false); 276 277 /* waiting for the utmi_clk to become stable */ 278 udelay(2000); 279 280 return 0; 281 } 282 283 static int rockchip_usb2phy_exit(struct phy *phy) 284 { 285 struct udevice *parent = phy->dev->parent; 286 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 287 const struct rockchip_usb2phy_port_cfg *port_cfg; 288 289 if (phy->id == USB2PHY_PORT_OTG) { 290 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 291 } else if (phy->id == USB2PHY_PORT_HOST) { 292 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 293 } else { 294 dev_err(phy->dev, "phy id %lu not support", phy->id); 295 return -EINVAL; 296 } 297 298 property_enable(rphy->grf, &port_cfg->phy_sus, true); 299 300 return 0; 301 } 302 303 static int rockchip_usb2phy_of_xlate(struct phy *phy, 304 struct ofnode_phandle_args *args) 305 { 306 const char *dev_name = phy->dev->name; 307 308 if (!strcasecmp(dev_name, "host-port")) { 309 phy->id = USB2PHY_PORT_HOST; 310 } else if (!strcasecmp(dev_name, "otg-port")) { 311 phy->id = USB2PHY_PORT_OTG; 312 } else { 313 pr_err("%s: invalid dev name\n", __func__); 314 return -EINVAL; 315 } 316 317 return 0; 318 } 319 320 static int rockchip_usb2phy_bind(struct udevice *dev) 321 { 322 struct udevice *child; 323 ofnode subnode; 324 const char *node_name; 325 int ret; 326 327 dev_for_each_subnode(subnode, dev) { 328 if (!ofnode_valid(subnode)) { 329 debug("%s: %s subnode not found", __func__, dev->name); 330 return -ENXIO; 331 } 332 333 node_name = ofnode_get_name(subnode); 334 debug("%s: subnode %s\n", __func__, node_name); 335 336 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 337 node_name, subnode, &child); 338 if (ret) { 339 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 340 __func__, node_name); 341 return ret; 342 } 343 } 344 345 return 0; 346 } 347 348 static int rockchip_usb2phy_probe(struct udevice *dev) 349 { 350 const struct rockchip_usb2phy_cfg *phy_cfgs; 351 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 352 u32 reg, index; 353 354 rphy->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 355 356 /* get phy power reset control */ 357 if (reset_get_by_name(dev, "u2phy", rphy->reset)) { 358 pr_err("can't get phy power reset for %s", dev->name); 359 return -EINVAL; 360 } 361 362 if (rphy->grf <= 0) { 363 dev_err(dev, "get syscon grf failed\n"); 364 return -EINVAL; 365 } 366 367 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 368 dev_err(dev, "could not read reg\n"); 369 return -EINVAL; 370 } 371 372 phy_cfgs = 373 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 374 if (!phy_cfgs) { 375 dev_err(dev, "unable to get phy_cfgs\n"); 376 return -EINVAL; 377 } 378 379 /* find out a proper config which can be matched with dt. */ 380 index = 0; 381 do { 382 if (phy_cfgs[index].reg == reg) { 383 rphy->phy_cfg = &phy_cfgs[index]; 384 break; 385 } 386 } while (!phy_cfgs[index++].last); 387 388 if (!rphy->phy_cfg) { 389 dev_err(dev, "no phy-config can be matched\n"); 390 return -EINVAL; 391 } 392 393 if (rphy->phy_cfg->phy_tuning) 394 rphy->phy_cfg->phy_tuning(rphy); 395 396 return 0; 397 } 398 399 static int rv1126_usb2phy_tuning(struct rockchip_usb2phy *rphy) 400 { 401 return 0; 402 } 403 404 static struct phy_ops rockchip_usb2phy_ops = { 405 .init = rockchip_usb2phy_init, 406 .exit = rockchip_usb2phy_exit, 407 .of_xlate = rockchip_usb2phy_of_xlate, 408 }; 409 410 static const struct rockchip_usb2phy_cfg rv1126_phy_cfgs[] = { 411 { 412 .reg = 0xff4c0000, 413 .num_ports = 1, 414 .phy_tuning = rv1126_usb2phy_tuning, 415 .clkout_ctl = { 0x10230, 14, 14, 0, 1 }, 416 .port_cfgs = { 417 [USB2PHY_PORT_OTG] = { 418 .bypass_otgsuspendm = { 0x10234, 12, 12, 0, 1 }, 419 .bvalidfall_det_en = { 0x10300, 3, 3, 0, 1 }, 420 .bvalidfall_det_st = { 0x10304, 3, 3, 0, 1 }, 421 .bvalidfall_det_clr = { 0x10308, 3, 3, 0, 1 }, 422 .bvalidrise_det_en = { 0x10300, 2, 2, 0, 1 }, 423 .bvalidrise_det_st = { 0x10304, 2, 2, 0, 1 }, 424 .bvalidrise_det_clr = { 0x10308, 2, 2, 0, 1 }, 425 .disconfall_det_en = { 0x10300, 7, 7, 0, 1 }, 426 .disconfall_det_st = { 0x10304, 7, 7, 0, 1 }, 427 .disconfall_det_clr = { 0x10308, 7, 7, 0, 1 }, 428 .disconrise_det_en = { 0x10300, 6, 6, 0, 1 }, 429 .disconrise_det_st = { 0x10304, 6, 6, 0, 1 }, 430 .disconrise_det_clr = { 0x10308, 6, 6, 0, 1 }, 431 .idfall_det_en = { 0x10300, 5, 5, 0, 1 }, 432 .idfall_det_st = { 0x10304, 5, 5, 0, 1 }, 433 .idfall_det_clr = { 0x10308, 5, 5, 0, 1 }, 434 .idpullup = { 0x10230, 11, 11, 0, 1 }, 435 .idrise_det_en = { 0x10300, 4, 4, 0, 1 }, 436 .idrise_det_st = { 0x10304, 4, 4, 0, 1 }, 437 .idrise_det_clr = { 0x10308, 4, 4, 0, 1 }, 438 .ls_det_en = { 0x10300, 0, 0, 0, 1 }, 439 .ls_det_st = { 0x10304, 0, 0, 0, 1 }, 440 .ls_det_clr = { 0x10308, 0, 0, 0, 1 }, 441 .phy_sus = { 0x10230, 8, 0, 0x052, 0x1d9 }, 442 .utmi_bvalid = { 0x10248, 9, 9, 0, 1 }, 443 .utmi_iddig = { 0x10248, 6, 6, 0, 1 }, 444 .utmi_hostdet = { 0x10248, 7, 7, 0, 1 }, 445 } 446 }, 447 .chg_det = { 448 .chg_en = { 0x10234, 14, 14, 0, 1 }, 449 .chg_rst = { 0x10234, 15, 15, 0, 1 }, 450 .chg_valid = { 0x10248, 12, 12, 0, 1 }, 451 .phy_connect = { 0x10248, 13, 13, 0, 1 }, 452 }, 453 }, 454 { 455 .reg = 0xff4c8000, 456 .num_ports = 1, 457 .phy_tuning = rv1126_usb2phy_tuning, 458 .clkout_ctl = { 0x10238, 9, 9, 0, 1 }, 459 .port_cfgs = { 460 [USB2PHY_PORT_HOST] = { 461 .disconfall_det_en = { 0x10300, 9, 9, 0, 1 }, 462 .disconfall_det_st = { 0x10304, 9, 9, 0, 1 }, 463 .disconfall_det_clr = { 0x10308, 9, 9, 0, 1 }, 464 .disconrise_det_en = { 0x10300, 8, 8, 0, 1 }, 465 .disconrise_det_st = { 0x10304, 8, 8, 0, 1 }, 466 .disconrise_det_clr = { 0x10308, 8, 8, 0, 1 }, 467 .ls_det_en = { 0x10300, 1, 1, 0, 1 }, 468 .ls_det_st = { 0x10304, 1, 1, 0, 1 }, 469 .ls_det_clr = { 0x10308, 1, 1, 0, 1 }, 470 .phy_sus = { 0x10238, 3, 0, 0x2, 0x9 }, 471 .utmi_hostdet = { 0x10248, 23, 23, 0, 1 }, 472 } 473 }, 474 .chg_det = { 475 .chg_en = { 0x10238, 7, 7, 0, 1 }, 476 .chg_rst = { 0x10238, 8, 8, 0, 1 }, 477 .chg_valid = { 0x10248, 28, 28, 0, 1 }, 478 .phy_connect = { 0x10248, 29, 29, 0, 1 }, 479 }, 480 .last = true, 481 }, 482 }; 483 484 static const struct udevice_id rockchip_usb2phy_ids[] = { 485 { .compatible = "rockchip,rv1126-usb2phy", .data = (ulong)&rv1126_phy_cfgs }, 486 { } 487 }; 488 489 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 490 .name = "rockchip_usb2phy_port", 491 .id = UCLASS_PHY, 492 .ops = &rockchip_usb2phy_ops, 493 }; 494 495 U_BOOT_DRIVER(rockchip_usb2phy) = { 496 .name = "rockchip_usb2phy", 497 .id = UCLASS_PHY, 498 .of_match = rockchip_usb2phy_ids, 499 .probe = rockchip_usb2phy_probe, 500 .bind = rockchip_usb2phy_bind, 501 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 502 }; 503