1 /* 2 * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/cru_px30.h> 11 #include <asm/arch/grf_px30.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/uart.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/cru_px30.h> 16 #include <dt-bindings/clock/px30-cru.h> 17 18 #define PMU_PWRDN_CON 0xff000018 19 #define GRF_CPU_CON1 0xff140504 20 21 #define VIDEO_PHY_BASE 0xff2e0000 22 #define FW_DDR_CON_REG 0xff534040 23 #define SERVICE_CORE_ADDR 0xff508000 24 #define QOS_PRIORITY 0x08 25 26 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 27 28 #ifdef CONFIG_ARM64 29 #include <asm/armv8/mmu.h> 30 31 static struct mm_region px30_mem_map[] = { 32 { 33 .virt = 0x0UL, 34 .phys = 0x0UL, 35 .size = 0xff000000UL, 36 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 37 PTE_BLOCK_INNER_SHARE 38 }, { 39 .virt = 0xff000000UL, 40 .phys = 0xff000000UL, 41 .size = 0x01000000UL, 42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 43 PTE_BLOCK_NON_SHARE | 44 PTE_BLOCK_PXN | PTE_BLOCK_UXN 45 }, { 46 /* List terminator */ 47 0, 48 } 49 }; 50 51 struct mm_region *mem_map = px30_mem_map; 52 #endif 53 54 #define PMU_PWRDN_CON 0xff000018 55 #define GRF_BASE 0xff140000 56 #define CRU_BASE 0xff2b0000 57 #define VIDEO_PHY_BASE 0xff2e0000 58 #define SERVICE_CORE_ADDR 0xff508000 59 #define DDR_FW_BASE 0xff534000 60 61 #define FW_DDR_CON 0x40 62 63 #define QOS_PRIORITY 0x08 64 65 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) 66 67 /* GRF_GPIO1CL_IOMUX */ 68 enum { 69 GPIO1C1_SHIFT = 4, 70 GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT, 71 GPIO1C1_GPIO = 0, 72 GPIO1C1_UART1_TX, 73 74 GPIO1C0_SHIFT = 0, 75 GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT, 76 GPIO1C0_GPIO = 0, 77 GPIO1C0_UART1_RX, 78 }; 79 80 /* GRF_GPIO1DL_IOMUX */ 81 enum { 82 GPIO1D3_SHIFT = 12, 83 GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, 84 GPIO1D3_GPIO = 0, 85 GPIO1D3_SDMMC_D1, 86 GPIO1D3_UART2_RXM0, 87 88 GPIO1D2_SHIFT = 8, 89 GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, 90 GPIO1D2_GPIO = 0, 91 GPIO1D2_SDMMC_D0, 92 GPIO1D2_UART2_TXM0, 93 }; 94 95 /* GRF_GPIO1DH_IOMUX */ 96 enum { 97 GPIO1D7_SHIFT = 12, 98 GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT, 99 GPIO1D7_GPIO = 0, 100 GPIO1D7_SDMMC_CMD, 101 102 GPIO1D6_SHIFT = 8, 103 GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT, 104 GPIO1D6_GPIO = 0, 105 GPIO1D6_SDMMC_CLK, 106 107 GPIO1D5_SHIFT = 4, 108 GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT, 109 GPIO1D5_GPIO = 0, 110 GPIO1D5_SDMMC_D3, 111 112 GPIO1D4_SHIFT = 0, 113 GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT, 114 GPIO1D4_GPIO = 0, 115 GPIO1D4_SDMMC_D2, 116 }; 117 118 /* GRF_GPIO2BH_IOMUX */ 119 enum { 120 GPIO2B6_SHIFT = 8, 121 GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT, 122 GPIO2B6_GPIO = 0, 123 GPIO2B6_CIF_D1M0, 124 GPIO2B6_UART2_RXM1, 125 126 GPIO2B4_SHIFT = 0, 127 GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT, 128 GPIO2B4_GPIO = 0, 129 GPIO2B4_CIF_D0M0, 130 GPIO2B4_UART2_TXM1, 131 }; 132 133 /* GRF_GPIO3AL_IOMUX */ 134 enum { 135 GPIO3A2_SHIFT = 8, 136 GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT, 137 GPIO3A2_GPIO = 0, 138 GPIO3A2_UART5_TX = 4, 139 140 GPIO3A1_SHIFT = 4, 141 GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT, 142 GPIO3A1_GPIO = 0, 143 GPIO3A1_UART5_RX = 4, 144 }; 145 146 enum { 147 IOVSEL6_CTRL_SHIFT = 0, 148 IOVSEL6_CTRL_MASK = BIT(0), 149 VCCIO6_SEL_BY_GPIO = 0, 150 VCCIO6_SEL_BY_IOVSEL6, 151 152 IOVSEL6_SHIFT = 1, 153 IOVSEL6_MASK = BIT(1), 154 VCCIO6_3V3 = 0, 155 VCCIO6_1V8, 156 }; 157 158 /* 159 * The voltage of VCCIO6(which is the voltage domain of emmc/flash/sfc 160 * interface) can indicated by GPIO0_B6 or io_vsel6. The SOC defaults 161 * use GPIO0_B6 to indicate power supply voltage for VCCIO6 by hardware, 162 * then we can switch to io_vsel6 after system power on, and release GPIO0_B6 163 * for other usage. 164 */ 165 166 #define GPIO0_B6 14 167 #define GPIO0_BASE 0xff040000 168 #define GPIO_SWPORTA_DDR 0x4 169 #define GPIO_EXT_PORTA 0x50 170 171 static int grf_vccio6_vsel_init(void) 172 { 173 static struct px30_grf * const grf = (void *)GRF_BASE; 174 u32 val; 175 176 val = readl(GPIO0_BASE + GPIO_SWPORTA_DDR); 177 val &= ~BIT(GPIO0_B6); 178 writel(val, GPIO0_BASE + GPIO_SWPORTA_DDR); 179 180 if (readl(GPIO0_BASE + GPIO_EXT_PORTA) & BIT(GPIO0_B6)) 181 val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT | 182 VCCIO6_1V8 << IOVSEL6_SHIFT; 183 else 184 val = VCCIO6_SEL_BY_IOVSEL6 << IOVSEL6_CTRL_SHIFT | 185 VCCIO6_3V3 << IOVSEL6_SHIFT; 186 rk_clrsetreg(&grf->io_vsel, IOVSEL6_CTRL_MASK | IOVSEL6_MASK, val); 187 188 return 0; 189 } 190 191 int arch_cpu_init(void) 192 { 193 #ifdef CONFIG_SPL_BUILD 194 /* We do some SoC one time setting here. */ 195 /* Disable the ddr secure region setting to make it non-secure */ 196 writel(0x0, FW_DDR_CON_REG); 197 #endif 198 /* Enable PD_VO (default disable at reset) */ 199 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 200 201 #ifdef CONFIG_SPL_BUILD 202 /* Set cpu qos priority */ 203 writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY); 204 205 #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \ 206 (CONFIG_DEBUG_UART_BASE != 0xff160000) || \ 207 (CONFIG_DEBUG_UART_CHANNEL != 0) 208 static struct px30_grf * const grf = (void *)GRF_BASE; 209 /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */ 210 rk_clrsetreg(&grf->gpio1dl_iomux, 211 GPIO1D3_MASK | GPIO1D2_MASK, 212 GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT | 213 GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT); 214 rk_clrsetreg(&grf->gpio1dh_iomux, 215 GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK, 216 GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT | 217 GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT | 218 GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT | 219 GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT); 220 #endif 221 222 #endif 223 224 /* Enable PD_VO (default disable at reset) */ 225 rk_clrreg(PMU_PWRDN_CON, 1 << 13); 226 227 /* Disable video phy bandgap by default */ 228 writel(0x82, VIDEO_PHY_BASE + 0x0000); 229 writel(0x05, VIDEO_PHY_BASE + 0x03ac); 230 231 /* Clear the force_jtag */ 232 rk_clrreg(GRF_CPU_CON1, 1 << 7); 233 234 grf_vccio6_vsel_init(); 235 236 return 0; 237 } 238 239 #define GRF_BASE 0xff140000 240 #define UART2_BASE 0xff160000 241 #define CRU_BASE 0xff2b0000 242 void board_debug_uart_init(void) 243 { 244 static struct px30_grf * const grf = (void *)GRF_BASE; 245 static struct px30_cru * const cru = (void *)CRU_BASE; 246 247 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000) 248 /* uart_sel_clk default select 24MHz */ 249 rk_clrsetreg(&cru->clksel_con[34], 250 UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK, 251 UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0); 252 rk_clrsetreg(&cru->clksel_con[35], 253 UART1_CLK_SEL_MASK, 254 UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT); 255 256 rk_clrsetreg(&grf->gpio1cl_iomux, 257 GPIO1C1_MASK | GPIO1C0_MASK, 258 GPIO1C1_UART1_TX << GPIO1C1_SHIFT | 259 GPIO1C0_UART1_RX << GPIO1C0_SHIFT); 260 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000) 261 /* uart_sel_clk default select 24MHz */ 262 rk_clrsetreg(&cru->clksel_con[46], 263 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, 264 UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0); 265 rk_clrsetreg(&cru->clksel_con[47], 266 UART5_CLK_SEL_MASK, 267 UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT); 268 269 rk_clrsetreg(&grf->gpio3al_iomux, 270 GPIO3A2_MASK | GPIO3A1_MASK, 271 GPIO3A2_UART5_TX << GPIO3A2_SHIFT | 272 GPIO3A1_UART5_RX << GPIO3A1_SHIFT); 273 #else 274 /* GRF_IOFUNC_CON0 */ 275 enum { 276 CON_IOMUX_UART2SEL_SHIFT = 10, 277 CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, 278 CON_IOMUX_UART2SEL_M0 = 0, 279 CON_IOMUX_UART2SEL_M1, 280 CON_IOMUX_UART2SEL_USBPHY, 281 }; 282 283 /* uart_sel_clk default select 24MHz */ 284 rk_clrsetreg(&cru->clksel_con[37], 285 UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK, 286 UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0); 287 rk_clrsetreg(&cru->clksel_con[38], 288 UART2_CLK_SEL_MASK, 289 UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); 290 291 #if (CONFIG_DEBUG_UART2_CHANNEL == 1) 292 /* Enable early UART2 */ 293 rk_clrsetreg(&grf->iofunc_con0, 294 CON_IOMUX_UART2SEL_MASK, 295 CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT); 296 297 /* 298 * Set iomux to UART2_M0 and UART2_M1. 299 * Because uart2_rxm0 and uart2_txm0 are default reset value, 300 * so only need set uart2_rxm1 and uart2_txm1 here. 301 */ 302 rk_clrsetreg(&grf->gpio2bh_iomux, 303 GPIO2B6_MASK | GPIO2B4_MASK, 304 GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT | 305 GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT); 306 #else 307 rk_clrsetreg(&grf->iofunc_con0, 308 CON_IOMUX_UART2SEL_MASK, 309 CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); 310 311 rk_clrsetreg(&grf->gpio1dl_iomux, 312 GPIO1D3_MASK | GPIO1D2_MASK, 313 GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | 314 GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); 315 #endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */ 316 317 #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ 318 } 319 320 int set_armclk_rate(void) 321 { 322 struct px30_clk_priv *priv; 323 struct clk clk; 324 int ret; 325 326 ret = rockchip_get_clk(&clk.dev); 327 if (ret) { 328 printf("Failed to get clk dev\n"); 329 return ret; 330 } 331 clk.id = ARMCLK; 332 priv = dev_get_priv(clk.dev); 333 ret = clk_set_rate(&clk, priv->armclk_hz); 334 if (ret < 0) { 335 printf("Failed to set armclk %lu\n", priv->armclk_hz); 336 return ret; 337 } 338 priv->set_armclk_rate = true; 339 340 return 0; 341 } 342