1/* 2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; 16 }; 17 18 secure-otp@ffcd0000 { 19 compatible = "rockchip,rk3528-secure-otp"; 20 reg = <0x0 0xffcd0000 0x0 0x4000>; 21 secure_conf = <0xff4500c0>; 22 mask_addr = <0x0>; 23 cru_rst_addr = <0xff4a8080>; 24 u-boot,dm-spl; 25 status = "okay"; 26 }; 27 28}; 29 30&grf { 31 u-boot,dm-spl; 32 status = "okay"; 33}; 34 35&ioc_grf { 36 u-boot,dm-spl; 37 status = "okay"; 38}; 39 40&combphy_pu { 41 u-boot,dm-pre-reloc; 42 status = "okay"; 43}; 44 45&cru { 46 /delete-property/ assigned-clocks; 47 /delete-property/ assigned-clock-rates; 48 u-boot,dm-spl; 49 status = "okay"; 50}; 51 52&crypto { 53 u-boot,dm-spl; 54 status = "okay"; 55}; 56 57&rng { 58 u-boot,dm-pre-reloc; 59 status = "okay"; 60}; 61 62&psci { 63 u-boot,dm-pre-reloc; 64 status = "okay"; 65}; 66 67&uart2 { 68 clock-frequency = <24000000>; 69 u-boot,dm-spl; 70 status = "okay"; 71}; 72 73&sfc { 74 u-boot,dm-spl; 75 /delete-property/ pinctrl-names; 76 /delete-property/ pinctrl-0; 77 /delete-property/ assigned-clocks; 78 /delete-property/ assigned-clock-rates; 79 status = "okay"; 80 81 #address-cells = <1>; 82 #size-cells = <0>; 83 spi_nand: flash@0 { 84 u-boot,dm-spl; 85 compatible = "spi-nand"; 86 reg = <0>; 87 spi-tx-bus-width = <1>; 88 spi-rx-bus-width = <4>; 89 spi-max-frequency = <75000000>; 90 }; 91 92 spi_nor: flash@1 { 93 u-boot,dm-spl; 94 compatible = "jedec,spi-nor"; 95 label = "sfc_nor"; 96 reg = <0>; 97 spi-tx-bus-width = <1>; 98 spi-rx-bus-width = <4>; 99 spi-max-frequency = <100000000>; 100 }; 101}; 102 103&sdhci { 104 bus-width = <8>; 105 u-boot,dm-spl; 106 /delete-property/ assigned-clocks; 107 /delete-property/ assigned-clock-rates; 108 /delete-property/ pinctrl-names; 109 /delete-property/ pinctrl-0; 110 mmc-hs400-1_8v; 111 mmc-hs400-enhanced-strobe; 112 fixed-emmc-driver-type = <1>; 113 status = "okay"; 114}; 115 116&sdmmc { 117 u-boot,dm-spl; 118 status = "okay"; 119}; 120 121&saradc { 122 u-boot,dm-pre-reloc; 123 status = "okay"; 124}; 125 126&u2phy_otg { 127 u-boot,dm-pre-reloc; 128 status = "okay"; 129}; 130 131&usb2phy { 132 u-boot,dm-pre-reloc; 133 status = "okay"; 134}; 135 136&firmware { 137 u-boot,dm-spl; 138}; 139 140&scmi { 141 u-boot,dm-spl; 142}; 143 144&scmi_clk { 145 u-boot,dm-spl; 146}; 147 148&scmi_shmem { 149 u-boot,dm-spl; 150}; 151 152&pinctrl { 153 u-boot,dm-spl; 154 status = "okay"; 155}; 156 157&gpio0 { 158 u-boot,dm-spl; 159}; 160 161&gpio1 { 162 u-boot,dm-spl; 163}; 164 165&gpio2 { 166 u-boot,dm-spl; 167}; 168 169/* Avaliable for PCIe */ 170&gpio3 { 171 u-boot,dm-pre-reloc; 172}; 173 174/* Avaliable for PCIe */ 175&gpio4 { 176 u-boot,dm-pre-reloc; 177}; 178 179&pcfg_pull_none_drv_level_1 { 180 u-boot,dm-spl; 181}; 182 183&pcfg_pull_none_drv_level_2 { 184 u-boot,dm-spl; 185}; 186 187&pcfg_pull_up_drv_level_1 { 188 u-boot,dm-spl; 189}; 190 191&pcfg_pull_up_drv_level_2 { 192 u-boot,dm-spl; 193}; 194 195&pcfg_pull_up { 196 u-boot,dm-spl; 197}; 198 199&pcfg_pull_none { 200 u-boot,dm-spl; 201}; 202 203&sdmmc_pins { 204 u-boot,dm-spl; 205}; 206 207&sdmmc_bus4 { 208 u-boot,dm-spl; 209}; 210 211&sdmmc_clk { 212 u-boot,dm-spl; 213}; 214 215&sdmmc_cmd { 216 u-boot,dm-spl; 217}; 218 219&sdmmc_det { 220 u-boot,dm-spl; 221}; 222