1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3036.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3036-cru.h> 18 #include <linux/log2.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 2400U * 1000000, 24 VCO_MIN_HZ = 600 * 1000000, 25 OUTPUT_MAX_HZ = 2400U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #ifndef CONFIG_SPL_BUILD 30 #define RK3036_CLK_DUMP(_id, _name, _iscru) \ 31 { \ 32 .id = _id, \ 33 .name = _name, \ 34 .is_cru = _iscru, \ 35 } 36 37 static const struct rk3036_clk_info clks_dump[] = { 38 RK3036_CLK_DUMP(PLL_APLL, "apll", true), 39 RK3036_CLK_DUMP(PLL_DPLL, "dpll", true), 40 RK3036_CLK_DUMP(PLL_GPLL, "gpll", true), 41 }; 42 #endif 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 47 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 48 49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 50 .refdiv = _refdiv,\ 51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ 53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ 54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ 55 #hz "Hz cannot be hit with PLL "\ 56 "divisors on line " __stringify(__LINE__)); 57 58 /* use integer mode*/ 59 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 60 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 61 62 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, 63 const struct pll_div *div) 64 { 65 int pll_id = rk_pll_id(clk_id); 66 struct rk3036_pll *pll = &cru->pll[pll_id]; 67 68 /* All PLLs have same VCO and output frequency range restrictions. */ 69 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 70 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 71 72 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\ 73 vco=%u Hz, output=%u Hz\n", 74 pll, div->fbdiv, div->refdiv, div->postdiv1, 75 div->postdiv2, vco_hz, output_hz); 76 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 77 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 78 79 /* use integer mode */ 80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 81 82 /* Power down */ 83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 84 85 rk_clrsetreg(&pll->con0, 86 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 87 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 90 div->refdiv << PLL_REFDIV_SHIFT)); 91 92 /* Power Up */ 93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 94 95 /* waiting for pll lock */ 96 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 97 udelay(1); 98 99 return 0; 100 } 101 102 static void rkclk_init(struct rk3036_cru *cru) 103 { 104 u32 aclk_div; 105 u32 hclk_div; 106 u32 pclk_div; 107 u32 nandc_div; 108 109 /* pll enter slow-mode */ 110 rk_clrsetreg(&cru->cru_mode_con, 111 GPLL_MODE_MASK | APLL_MODE_MASK, 112 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 113 APLL_MODE_SLOW << APLL_MODE_SHIFT); 114 115 /* init pll */ 116 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 117 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 118 119 /* 120 * select apll as cpu/core clock pll source and 121 * set up dependent divisors for PERI and ACLK clocks. 122 * core hz : apll = 1:1 123 */ 124 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 125 assert((aclk_div + 1) * CORE_ACLK_HZ <= APLL_HZ && aclk_div < 0x7); 126 127 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 128 assert((pclk_div + 1) * CORE_PERI_HZ <= APLL_HZ && pclk_div < 0xf); 129 130 rk_clrsetreg(&cru->cru_clksel_con[0], 131 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 132 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 133 0 << CORE_DIV_CON_SHIFT); 134 135 rk_clrsetreg(&cru->cru_clksel_con[1], 136 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 137 aclk_div << CORE_ACLK_DIV_SHIFT | 138 pclk_div << CORE_PERI_DIV_SHIFT); 139 140 /* 141 * select gpll as pd_bus bus clock source and 142 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 143 */ 144 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 145 assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f); 146 147 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 148 assert((pclk_div + 1) * BUS_PCLK_HZ <= BUS_ACLK_HZ && pclk_div <= 0x7); 149 150 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 151 assert((hclk_div + 1) * BUS_HCLK_HZ <= BUS_ACLK_HZ && hclk_div <= 0x3); 152 153 rk_clrsetreg(&cru->cru_clksel_con[0], 154 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 155 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 156 aclk_div << BUS_ACLK_DIV_SHIFT); 157 158 rk_clrsetreg(&cru->cru_clksel_con[1], 159 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 160 pclk_div << BUS_PCLK_DIV_SHIFT | 161 hclk_div << BUS_HCLK_DIV_SHIFT); 162 163 /* 164 * select gpll as pd_peri bus clock source and 165 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 166 */ 167 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 168 assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f); 169 170 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 171 assert((1 << hclk_div) * PERI_HCLK_HZ <= 172 PERI_ACLK_HZ && (hclk_div < 0x4)); 173 174 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 175 assert((1 << pclk_div) * PERI_PCLK_HZ <= 176 PERI_ACLK_HZ && pclk_div < 0x8); 177 178 rk_clrsetreg(&cru->cru_clksel_con[10], 179 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 180 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 181 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 182 pclk_div << PERI_PCLK_DIV_SHIFT | 183 hclk_div << PERI_HCLK_DIV_SHIFT | 184 aclk_div << PERI_ACLK_DIV_SHIFT); 185 186 nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000); 187 188 rk_clrsetreg(&cru->cru_clksel_con[16], 189 NANDC_PLL_MASK | NANDC_DIV_MASK, 190 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 191 nandc_div << NANDC_DIV_SHIFT); 192 193 /* PLL enter normal-mode */ 194 rk_clrsetreg(&cru->cru_mode_con, 195 GPLL_MODE_MASK | APLL_MODE_MASK, 196 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 197 APLL_MODE_NORM << APLL_MODE_SHIFT); 198 } 199 200 /* Get pll rate by id */ 201 static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, 202 enum rk_clk_id clk_id) 203 { 204 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 205 uint32_t con; 206 int pll_id = rk_pll_id(clk_id); 207 struct rk3036_pll *pll = &cru->pll[pll_id]; 208 static u8 clk_shift[CLK_COUNT] = { 209 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 210 GPLL_MODE_SHIFT, 0xff 211 }; 212 static u32 clk_mask[CLK_COUNT] = { 213 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff, 214 GPLL_MODE_MASK, 0xffffffff 215 }; 216 uint shift; 217 uint mask; 218 219 con = readl(&cru->cru_mode_con); 220 shift = clk_shift[clk_id]; 221 mask = clk_mask[clk_id]; 222 223 switch ((con & mask) >> shift) { 224 case GPLL_MODE_SLOW: 225 return OSC_HZ; 226 case GPLL_MODE_NORM: 227 228 /* normal mode */ 229 con = readl(&pll->con0); 230 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 231 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 232 con = readl(&pll->con1); 233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 234 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 235 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 236 case GPLL_MODE_DEEP: 237 default: 238 return 32768; 239 } 240 } 241 242 static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, 243 int periph) 244 { 245 uint src_rate; 246 uint div, mux; 247 u32 con; 248 249 switch (periph) { 250 case HCLK_EMMC: 251 case SCLK_EMMC: 252 con = readl(&cru->cru_clksel_con[12]); 253 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 254 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 255 break; 256 case HCLK_SDIO: 257 case SCLK_SDIO: 258 con = readl(&cru->cru_clksel_con[12]); 259 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 260 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 261 break; 262 default: 263 return -EINVAL; 264 } 265 266 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 267 return DIV_TO_RATE(src_rate, div) / 2; 268 } 269 270 static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, 271 int periph, uint freq) 272 { 273 int src_clk_div; 274 int mux; 275 276 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 277 278 /* mmc clock auto divide 2 in internal */ 279 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 280 281 if (src_clk_div > 128) { 282 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 283 assert(src_clk_div - 1 < 128); 284 mux = EMMC_SEL_24M; 285 } else { 286 mux = EMMC_SEL_GPLL; 287 } 288 289 switch (periph) { 290 case HCLK_EMMC: 291 case SCLK_EMMC: 292 rk_clrsetreg(&cru->cru_clksel_con[12], 293 EMMC_PLL_MASK | EMMC_DIV_MASK, 294 mux << EMMC_PLL_SHIFT | 295 (src_clk_div - 1) << EMMC_DIV_SHIFT); 296 break; 297 case HCLK_SDIO: 298 case SCLK_SDIO: 299 rk_clrsetreg(&cru->cru_clksel_con[11], 300 MMC0_PLL_MASK | MMC0_DIV_MASK, 301 mux << MMC0_PLL_SHIFT | 302 (src_clk_div - 1) << MMC0_DIV_SHIFT); 303 break; 304 default: 305 return -EINVAL; 306 } 307 308 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 309 } 310 311 static ulong rk3036_spi_get_clk(struct rk3036_cru *cru, uint clk_general_rate) 312 { 313 u32 div, con; 314 315 con = readl(&cru->cru_clksel_con[25]); 316 div = (con & SPI_DIV_MASK) >> SPI_DIV_SHIFT; 317 318 return DIV_TO_RATE(clk_general_rate, div); 319 } 320 321 static ulong rk3036_spi_set_clk(struct rk3036_cru *cru, 322 uint clk_general_rate, 323 ulong hz) 324 { 325 int div; 326 327 div = DIV_ROUND_UP(clk_general_rate, hz); 328 assert(div - 1 < 128); 329 rk_clrsetreg(&cru->cru_clksel_con[25], 330 SPI_PLL_SEL_MASK | SPI_DIV_MASK, 331 SPI_PLL_SEL_GPLL << SPI_PLL_SEL_SHIFT | 332 (div - 1) << SPI_DIV_SHIFT); 333 return rk3036_spi_get_clk(cru, clk_general_rate); 334 } 335 336 static ulong rockchip_dclk_lcdc_get_clk(struct rk3036_cru *cru, 337 uint clk_general_rate) 338 { 339 u32 con, div, sel, parent; 340 341 con = readl(&cru->cru_clksel_con[28]); 342 div = (con & LCDC_DCLK_DIV_MASK) >> LCDC_DCLK_DIV_SHIFT; 343 sel = (con & LCDC_DCLK_SEL_MASK) >> LCDC_DCLK_SEL_SHIFT; 344 if (sel == LCDC_DCLK_SEL_GPLL) 345 parent = clk_general_rate; 346 else 347 return -ENOENT; 348 349 return DIV_TO_RATE(parent, div); 350 } 351 352 static ulong rockchip_dclk_lcdc_set_clk(struct rk3036_cru *cru, 353 uint clk_general_rate, uint freq) 354 { 355 int src_clk_div; 356 357 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); 358 assert(src_clk_div - 1 <= 255); 359 360 rk_clrsetreg(&cru->cru_clksel_con[28], 361 LCDC_DCLK_SEL_MASK | LCDC_DCLK_DIV_MASK, 362 LCDC_DCLK_SEL_GPLL << LCDC_DCLK_SEL_SHIFT | 363 (src_clk_div - 1) << LCDC_DCLK_DIV_SHIFT); 364 365 return rockchip_dclk_lcdc_get_clk(cru, clk_general_rate); 366 } 367 368 static ulong rockchip_aclk_lcdc_get_clk(struct rk3036_cru *cru, 369 uint clk_general_rate) 370 { 371 u32 con, div, sel, parent; 372 373 con = readl(&cru->cru_clksel_con[31]); 374 div = (con & LCDC_ACLK_DIV_MASK) >> LCDC_ACLK_DIV_SHIFT; 375 sel = (con & LCDC_ACLK_SEL_MASK) >> LCDC_ACLK_SEL_SHIFT; 376 if (sel == LCDC_ACLK_SEL_GPLL) 377 parent = clk_general_rate; 378 else 379 return -ENOENT; 380 381 return DIV_TO_RATE(parent, div); 382 } 383 384 static ulong rockchip_aclk_lcdc_set_clk(struct rk3036_cru *cru, 385 uint clk_general_rate, uint freq) 386 { 387 int src_clk_div; 388 389 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); 390 assert(src_clk_div - 1 <= 31); 391 392 rk_clrsetreg(&cru->cru_clksel_con[31], 393 LCDC_ACLK_SEL_MASK | LCDC_ACLK_DIV_MASK, 394 LCDC_ACLK_SEL_GPLL << LCDC_ACLK_SEL_SHIFT | 395 (src_clk_div - 1) << LCDC_ACLK_DIV_SHIFT); 396 397 return rockchip_aclk_lcdc_get_clk(cru, clk_general_rate); 398 } 399 400 static ulong rk3036_clk_get_rate(struct clk *clk) 401 { 402 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 403 ulong gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 404 405 switch (clk->id) { 406 case 0 ... 63: 407 return rkclk_pll_get_rate(priv->cru, clk->id); 408 case SCLK_LCDC: 409 return rockchip_dclk_lcdc_get_clk(priv->cru, gclk_rate); 410 case ACLK_LCDC: 411 return rockchip_aclk_lcdc_get_clk(priv->cru, gclk_rate); 412 case SCLK_SPI: 413 return rk3036_spi_get_clk(priv->cru, gclk_rate); 414 default: 415 return -ENOENT; 416 } 417 } 418 419 static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate) 420 { 421 struct rk3036_clk_priv *priv = dev_get_priv(clk->dev); 422 ulong new_rate, gclk_rate; 423 424 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 425 switch (clk->id) { 426 case 0 ... 63: 427 return 0; 428 case HCLK_EMMC: 429 case SCLK_EMMC: 430 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 431 clk->id, rate); 432 break; 433 case SCLK_LCDC: 434 new_rate = rockchip_dclk_lcdc_set_clk(priv->cru, gclk_rate, 435 rate); 436 break; 437 case ACLK_LCDC: 438 new_rate = rockchip_aclk_lcdc_set_clk(priv->cru, gclk_rate, 439 rate); 440 break; 441 case SCLK_SPI: 442 new_rate = rk3036_spi_set_clk(priv->cru, gclk_rate, 443 rate); 444 break; 445 default: 446 return -ENOENT; 447 } 448 449 return new_rate; 450 } 451 452 static struct clk_ops rk3036_clk_ops = { 453 .get_rate = rk3036_clk_get_rate, 454 .set_rate = rk3036_clk_set_rate, 455 }; 456 457 static int rk3036_clk_ofdata_to_platdata(struct udevice *dev) 458 { 459 struct rk3036_clk_priv *priv = dev_get_priv(dev); 460 461 priv->cru = dev_read_addr_ptr(dev); 462 463 return 0; 464 } 465 466 static int rk3036_clk_probe(struct udevice *dev) 467 { 468 struct rk3036_clk_priv *priv = dev_get_priv(dev); 469 470 priv->sync_kernel = false; 471 if (!priv->armclk_enter_hz) 472 priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru, 473 CLK_ARM); 474 rkclk_init(priv->cru); 475 if (!priv->armclk_init_hz) 476 priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru, 477 CLK_ARM); 478 479 return 0; 480 } 481 482 static int rk3036_clk_bind(struct udevice *dev) 483 { 484 int ret; 485 struct udevice *sys_child, *sf_child; 486 struct sysreset_reg *priv; 487 struct softreset_reg *sf_priv; 488 489 /* The reset driver does not have a device node, so bind it here */ 490 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 491 &sys_child); 492 if (ret) { 493 debug("Warning: No sysreset driver: ret=%d\n", ret); 494 } else { 495 priv = malloc(sizeof(struct sysreset_reg)); 496 priv->glb_srst_fst_value = offsetof(struct rk3036_cru, 497 cru_glb_srst_fst_value); 498 priv->glb_srst_snd_value = offsetof(struct rk3036_cru, 499 cru_glb_srst_snd_value); 500 sys_child->priv = priv; 501 } 502 503 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 504 dev_ofnode(dev), &sf_child); 505 if (ret) { 506 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 507 } else { 508 sf_priv = malloc(sizeof(struct softreset_reg)); 509 sf_priv->sf_reset_offset = offsetof(struct rk3036_cru, 510 cru_softrst_con[0]); 511 sf_priv->sf_reset_num = 9; 512 sf_child->priv = sf_priv; 513 } 514 515 return 0; 516 } 517 518 static const struct udevice_id rk3036_clk_ids[] = { 519 { .compatible = "rockchip,rk3036-cru" }, 520 { } 521 }; 522 523 U_BOOT_DRIVER(rockchip_rk3036_cru) = { 524 .name = "clk_rk3036", 525 .id = UCLASS_CLK, 526 .of_match = rk3036_clk_ids, 527 .priv_auto_alloc_size = sizeof(struct rk3036_clk_priv), 528 .ofdata_to_platdata = rk3036_clk_ofdata_to_platdata, 529 .ops = &rk3036_clk_ops, 530 .bind = rk3036_clk_bind, 531 .probe = rk3036_clk_probe, 532 }; 533 534 #ifndef CONFIG_SPL_BUILD 535 /** 536 * soc_clk_dump() - Print clock frequencies 537 * Returns zero on success 538 * 539 * Implementation for the clk dump command. 540 */ 541 int soc_clk_dump(void) 542 { 543 struct udevice *cru_dev; 544 struct rk3036_clk_priv *priv; 545 const struct rk3036_clk_info *clk_dump; 546 struct clk clk; 547 unsigned long clk_count = ARRAY_SIZE(clks_dump); 548 unsigned long rate; 549 int i, ret; 550 551 ret = uclass_get_device_by_driver(UCLASS_CLK, 552 DM_GET_DRIVER(rockchip_rk3036_cru), 553 &cru_dev); 554 if (ret) { 555 printf("%s failed to get cru device\n", __func__); 556 return ret; 557 } 558 559 priv = dev_get_priv(cru_dev); 560 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 561 priv->sync_kernel ? "sync kernel" : "uboot", 562 priv->armclk_enter_hz / 1000, 563 priv->armclk_init_hz / 1000, 564 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 565 priv->set_armclk_rate ? " KHz" : "N/A"); 566 for (i = 0; i < clk_count; i++) { 567 clk_dump = &clks_dump[i]; 568 if (clk_dump->name) { 569 clk.id = clk_dump->id; 570 if (clk_dump->is_cru) 571 ret = clk_request(cru_dev, &clk); 572 if (ret < 0) 573 return ret; 574 575 rate = clk_get_rate(&clk); 576 clk_free(&clk); 577 if (i == 0) { 578 if (rate < 0) 579 printf(" %s %s\n", clk_dump->name, 580 "unknown"); 581 else 582 printf(" %s %lu KHz\n", clk_dump->name, 583 rate / 1000); 584 } else { 585 if (rate < 0) 586 printf(" %s %s\n", clk_dump->name, 587 "unknown"); 588 else 589 printf(" %s %lu KHz\n", clk_dump->name, 590 rate / 1000); 591 } 592 } 593 } 594 595 return 0; 596 } 597 #endif 598 599