1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <bitfield.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <syscon.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_px30.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/io.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/px30-cru.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 3200U * 1000000, 24 VCO_MIN_HZ = 800 * 1000000, 25 OUTPUT_MAX_HZ = 3200U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define PX30_VOP_PLL_LIMIT 600000000 30 31 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ 32 _postdiv2, _dsmpd, _frac) \ 33 { \ 34 .rate = _rate##U, \ 35 .fbdiv = _fbdiv, \ 36 .postdiv1 = _postdiv1, \ 37 .refdiv = _refdiv, \ 38 .postdiv2 = _postdiv2, \ 39 .dsmpd = _dsmpd, \ 40 .frac = _frac, \ 41 } 42 43 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ 44 { \ 45 .rate = _rate##U, \ 46 .aclk_div = _aclk_div, \ 47 .pclk_div = _pclk_div, \ 48 } 49 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 51 52 #define PX30_CLK_DUMP(_id, _name, _iscru) \ 53 { \ 54 .id = _id, \ 55 .name = _name, \ 56 .is_cru = _iscru, \ 57 } 58 59 static struct pll_rate_table px30_pll_rates[] = { 60 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 61 PX30_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 62 PX30_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 63 PX30_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 64 PX30_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 65 PX30_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 66 PX30_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 67 PX30_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), 68 }; 69 70 static const struct px30_clk_info clks_dump[] = { 71 PX30_CLK_DUMP(PLL_APLL, "apll", true), 72 PX30_CLK_DUMP(PLL_DPLL, "dpll", true), 73 PX30_CLK_DUMP(PLL_CPLL, "cpll", true), 74 PX30_CLK_DUMP(PLL_NPLL, "npll", true), 75 PX30_CLK_DUMP(PLL_GPLL, "gpll", false), 76 PX30_CLK_DUMP(ACLK_BUS_PRE, "aclk_bus", true), 77 PX30_CLK_DUMP(HCLK_BUS_PRE, "hclk_bus", true), 78 PX30_CLK_DUMP(PCLK_BUS_PRE, "pclk_bus", true), 79 PX30_CLK_DUMP(ACLK_PERI_PRE, "aclk_peri", true), 80 PX30_CLK_DUMP(HCLK_PERI_PRE, "hclk_peri", true), 81 PX30_CLK_DUMP(PCLK_PMU_PRE, "pclk_pmu", false), 82 }; 83 84 static struct cpu_rate_table px30_cpu_rates[] = { 85 PX30_CPUCLK_RATE(1200000000, 1, 5), 86 PX30_CPUCLK_RATE(1008000000, 1, 5), 87 PX30_CPUCLK_RATE(816000000, 1, 3), 88 PX30_CPUCLK_RATE(600000000, 1, 3), 89 PX30_CPUCLK_RATE(408000000, 1, 1), 90 }; 91 92 static u8 pll_mode_shift[PLL_COUNT] = { 93 APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, 94 NPLL_MODE_SHIFT, GPLL_MODE_SHIFT 95 }; 96 static u32 pll_mode_mask[PLL_COUNT] = { 97 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK, 98 NPLL_MODE_MASK, GPLL_MODE_MASK 99 }; 100 101 static struct pll_rate_table auto_table; 102 103 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 104 enum px30_pll_id pll_id); 105 106 static struct pll_rate_table *pll_clk_set_by_auto(u32 drate) 107 { 108 struct pll_rate_table *rate = &auto_table; 109 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 110 u32 postdiv1, postdiv2 = 1; 111 u32 fref_khz; 112 u32 diff_khz, best_diff_khz; 113 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 114 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 115 u32 vco_khz; 116 u32 rate_khz = drate / KHz; 117 118 if (!drate) { 119 printf("%s: the frequency can't be 0 Hz\n", __func__); 120 return NULL; 121 } 122 123 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); 124 if (postdiv1 > max_postdiv1) { 125 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 126 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 127 } 128 129 vco_khz = rate_khz * postdiv1 * postdiv2; 130 131 if (vco_khz < (VCO_MIN_HZ / KHz) || vco_khz > (VCO_MAX_HZ / KHz) || 132 postdiv2 > max_postdiv2) { 133 printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n", 134 __func__, rate_khz); 135 return NULL; 136 } 137 138 rate->postdiv1 = postdiv1; 139 rate->postdiv2 = postdiv2; 140 141 best_diff_khz = vco_khz; 142 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 143 fref_khz = ref_khz / refdiv; 144 145 fbdiv = vco_khz / fref_khz; 146 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 147 continue; 148 diff_khz = vco_khz - fbdiv * fref_khz; 149 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 150 fbdiv++; 151 diff_khz = fref_khz - diff_khz; 152 } 153 154 if (diff_khz >= best_diff_khz) 155 continue; 156 157 best_diff_khz = diff_khz; 158 rate->refdiv = refdiv; 159 rate->fbdiv = fbdiv; 160 } 161 162 if (best_diff_khz > 4 * (MHz / KHz)) { 163 printf("%s: Failed to match output frequency %u bestis %u Hz\n", 164 __func__, rate_khz, 165 best_diff_khz * KHz); 166 return NULL; 167 } 168 169 return rate; 170 } 171 172 static const struct pll_rate_table *get_pll_settings(unsigned long rate) 173 { 174 unsigned int rate_count = ARRAY_SIZE(px30_pll_rates); 175 int i; 176 177 for (i = 0; i < rate_count; i++) { 178 if (rate == px30_pll_rates[i].rate) 179 return &px30_pll_rates[i]; 180 } 181 182 return pll_clk_set_by_auto(rate); 183 } 184 185 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) 186 { 187 unsigned int rate_count = ARRAY_SIZE(px30_cpu_rates); 188 int i; 189 190 for (i = 0; i < rate_count; i++) { 191 if (rate == px30_cpu_rates[i].rate) 192 return &px30_cpu_rates[i]; 193 } 194 195 return NULL; 196 } 197 198 /* 199 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 200 * Formulas also embedded within the Fractional PLL Verilog model: 201 * If DSMPD = 1 (DSM is disabled, "integer mode") 202 * FOUTVCO = FREF / REFDIV * FBDIV 203 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 204 * Where: 205 * FOUTVCO = Fractional PLL non-divided output frequency 206 * FOUTPOSTDIV = Fractional PLL divided output frequency 207 * (output of second post divider) 208 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 209 * REFDIV = Fractional PLL input reference clock divider 210 * FBDIV = Integer value programmed into feedback divide 211 * 212 */ 213 static int rkclk_set_pll(struct px30_pll *pll, unsigned int *mode, 214 enum px30_pll_id pll_id, 215 unsigned long drate) 216 { 217 const struct pll_rate_table *rate; 218 uint vco_hz, output_hz; 219 220 rate = get_pll_settings(drate); 221 if (!rate) { 222 printf("%s unsupport rate\n", __func__); 223 return -EINVAL; 224 } 225 226 /* All PLLs have same VCO and output frequency range restrictions. */ 227 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; 228 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; 229 230 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", 231 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, 232 rate->postdiv2, vco_hz, output_hz); 233 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 234 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 235 236 /* 237 * When power on or changing PLL setting, 238 * we must force PLL into slow mode to ensure output stable clock. 239 */ 240 rk_clrsetreg(mode, pll_mode_mask[pll_id], 241 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); 242 243 /* use integer mode */ 244 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 245 /* Power down */ 246 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 247 248 rk_clrsetreg(&pll->con0, 249 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 250 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); 251 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 252 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | 253 rate->refdiv << PLL_REFDIV_SHIFT)); 254 255 /* Power Up */ 256 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 257 258 /* waiting for pll lock */ 259 while (!(readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))) 260 udelay(1); 261 262 rk_clrsetreg(mode, pll_mode_mask[pll_id], 263 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); 264 265 return 0; 266 } 267 268 static uint32_t rkclk_pll_get_rate(struct px30_pll *pll, unsigned int *mode, 269 enum px30_pll_id pll_id) 270 { 271 u32 refdiv, fbdiv, postdiv1, postdiv2; 272 u32 con, shift, mask; 273 274 con = readl(mode); 275 shift = pll_mode_shift[pll_id]; 276 mask = pll_mode_mask[pll_id]; 277 278 switch ((con & mask) >> shift) { 279 case PLLMUX_FROM_XIN24M: 280 return OSC_HZ; 281 case PLLMUX_FROM_PLL: 282 /* normal mode */ 283 con = readl(&pll->con0); 284 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 285 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 286 con = readl(&pll->con1); 287 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 288 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 289 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 290 case PLLMUX_FROM_RTC32K: 291 default: 292 return 32768; 293 } 294 } 295 296 static ulong px30_i2c_get_clk(struct px30_clk_priv *priv, ulong clk_id) 297 { 298 struct px30_cru *cru = priv->cru; 299 u32 div, con; 300 301 switch (clk_id) { 302 case SCLK_I2C0: 303 con = readl(&cru->clksel_con[49]); 304 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 305 break; 306 case SCLK_I2C1: 307 con = readl(&cru->clksel_con[49]); 308 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 309 break; 310 case SCLK_I2C2: 311 con = readl(&cru->clksel_con[50]); 312 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 313 break; 314 case SCLK_I2C3: 315 con = readl(&cru->clksel_con[50]); 316 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 317 break; 318 default: 319 printf("do not support this i2c bus\n"); 320 return -EINVAL; 321 } 322 323 return DIV_TO_RATE(priv->gpll_hz, div); 324 } 325 326 static ulong px30_i2c_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 327 { 328 struct px30_cru *cru = priv->cru; 329 int src_clk_div; 330 331 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 332 assert(src_clk_div - 1 <= 127); 333 334 switch (clk_id) { 335 case SCLK_I2C0: 336 rk_clrsetreg(&cru->clksel_con[49], 337 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT | 338 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT, 339 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | 340 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT); 341 break; 342 case SCLK_I2C1: 343 rk_clrsetreg(&cru->clksel_con[49], 344 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT | 345 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT, 346 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | 347 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT); 348 break; 349 case SCLK_I2C2: 350 rk_clrsetreg(&cru->clksel_con[50], 351 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT | 352 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT, 353 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | 354 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT); 355 break; 356 case SCLK_I2C3: 357 rk_clrsetreg(&cru->clksel_con[50], 358 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT | 359 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT, 360 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | 361 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT); 362 break; 363 default: 364 printf("do not support this i2c bus\n"); 365 return -EINVAL; 366 } 367 368 return px30_i2c_get_clk(priv, clk_id); 369 } 370 371 /* 372 * calculate best rational approximation for a given fraction 373 * taking into account restricted register size, e.g. to find 374 * appropriate values for a pll with 5 bit denominator and 375 * 8 bit numerator register fields, trying to set up with a 376 * frequency ratio of 3.1415, one would say: 377 * 378 * rational_best_approximation(31415, 10000, 379 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 380 * 381 * you may look at given_numerator as a fixed point number, 382 * with the fractional part size described in given_denominator. 383 * 384 * for theoretical background, see: 385 * http://en.wikipedia.org/wiki/Continued_fraction 386 */ 387 static void rational_best_approximation( 388 unsigned long given_numerator, unsigned long given_denominator, 389 unsigned long max_numerator, unsigned long max_denominator, 390 unsigned long *best_numerator, unsigned long *best_denominator) 391 { 392 unsigned long n, d, n0, d0, n1, d1; 393 394 n = given_numerator; 395 d = given_denominator; 396 n0 = 0; 397 d1 = 0; 398 n1 = 1; 399 d0 = 1; 400 for (;;) { 401 unsigned long t, a; 402 403 if (n1 > max_numerator || d1 > max_denominator) { 404 n1 = n0; 405 d1 = d0; 406 break; 407 } 408 if (d == 0) 409 break; 410 t = d; 411 a = n / d; 412 d = n % d; 413 n = t; 414 t = n0 + a * n1; 415 n0 = n1; 416 n1 = t; 417 t = d0 + a * d1; 418 d0 = d1; 419 d1 = t; 420 } 421 *best_numerator = n1; 422 *best_denominator = d1; 423 } 424 425 static ulong px30_i2s_get_clk(struct px30_clk_priv *priv, ulong clk_id) 426 { 427 u32 con, fracdiv, gate; 428 u32 clk_src = GPLL_HZ / 2; 429 unsigned long m, n; 430 struct px30_cru *cru = priv->cru; 431 432 switch (clk_id) { 433 case SCLK_I2S1: 434 con = readl(&cru->clksel_con[30]); 435 fracdiv = readl(&cru->clksel_con[31]); 436 gate = readl(&cru->clkgate_con[10]); 437 n = fracdiv & CLK_I2S1_FRAC_NUMERATOR_MASK; 438 n >>= CLK_I2S1_FRAC_NUMERATOR_SHIFT; 439 m = fracdiv & CLK_I2S1_FRAC_DENOMINATOR_MASK; 440 m >>= CLK_I2S1_FRAC_DENOMINATOR_SHIFT; 441 debug("con30: 0x%x, gate: 0x%x, frac: 0x%x\n", 442 con, gate, fracdiv); 443 break; 444 default: 445 printf("do not support this i2s bus\n"); 446 return -EINVAL; 447 } 448 449 return clk_src * n / m; 450 } 451 452 static ulong px30_i2s_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 453 { 454 u32 clk_src; 455 unsigned long m, n, val; 456 struct px30_cru *cru = priv->cru; 457 458 clk_src = GPLL_HZ / 2; 459 rational_best_approximation(hz, clk_src, 460 GENMASK(16 - 1, 0), 461 GENMASK(16 - 1, 0), 462 &m, &n); 463 switch (clk_id) { 464 case SCLK_I2S1: 465 rk_clrsetreg(&cru->clksel_con[30], 466 CLK_I2S1_PLL_SEL_MASK, CLK_I2S1_PLL_SEL_GPLL); 467 rk_clrsetreg(&cru->clksel_con[30], 468 CLK_I2S1_DIV_CON_MASK, 0x1); 469 rk_clrsetreg(&cru->clksel_con[30], 470 CLK_I2S1_SEL_MASK, CLK_I2S1_SEL_FRAC); 471 val = m << CLK_I2S1_FRAC_NUMERATOR_SHIFT | n; 472 writel(val, &cru->clksel_con[31]); 473 rk_clrsetreg(&cru->clkgate_con[10], 474 CLK_I2S1_OUT_MCLK_PAD_MASK, 475 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 476 break; 477 default: 478 printf("do not support this i2s bus\n"); 479 return -EINVAL; 480 } 481 482 return px30_i2s_get_clk(priv, clk_id); 483 } 484 485 static ulong px30_i2s1_mclk_get_clk(struct px30_clk_priv *priv, ulong clk_id) 486 { 487 struct px30_cru *cru = priv->cru; 488 u32 con; 489 490 con = readl(&cru->clksel_con[30]); 491 492 if (con & CLK_I2S1_OUT_SEL_MASK) 493 return 12000000; 494 495 return px30_i2s_get_clk(priv, SCLK_I2S1); 496 } 497 498 static ulong px30_i2s1_mclk_set_clk(struct px30_clk_priv *priv, ulong clk_id, 499 ulong hz) 500 { 501 struct px30_cru *cru = priv->cru; 502 503 if (hz == 12000000) { 504 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, 505 CLK_I2S1_OUT_SEL_OSC); 506 } else { 507 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, 508 CLK_I2S1_OUT_SEL_I2S1); 509 px30_i2s_set_clk(priv, SCLK_I2S1, hz); 510 } 511 512 rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK, 513 CLK_I2S1_OUT_MCLK_PAD_ENABLE); 514 515 return px30_i2s1_mclk_get_clk(priv, clk_id); 516 } 517 518 static ulong px30_nandc_get_clk(struct px30_clk_priv *priv) 519 { 520 struct px30_cru *cru = priv->cru; 521 u32 div, con; 522 523 con = readl(&cru->clksel_con[15]); 524 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; 525 526 return DIV_TO_RATE(priv->gpll_hz, div); 527 } 528 529 static ulong px30_nandc_set_clk(struct px30_clk_priv *priv, 530 ulong set_rate) 531 { 532 struct px30_cru *cru = priv->cru; 533 int src_clk_div; 534 535 /* Select nandc source from GPLL by default */ 536 /* nandc clock defaulg div 2 internal, need provide double in cru */ 537 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 538 assert(src_clk_div - 1 <= 31); 539 540 rk_clrsetreg(&cru->clksel_con[15], 541 NANDC_CLK_SEL_MASK | NANDC_PLL_MASK | 542 NANDC_DIV_MASK, 543 NANDC_CLK_SEL_NANDC << NANDC_CLK_SEL_SHIFT | 544 NANDC_SEL_GPLL << NANDC_PLL_SHIFT | 545 (src_clk_div - 1) << NANDC_DIV_SHIFT); 546 547 return px30_nandc_get_clk(priv); 548 } 549 550 static ulong px30_mmc_get_clk(struct px30_clk_priv *priv, uint clk_id) 551 { 552 struct px30_cru *cru = priv->cru; 553 u32 div, con, con_id; 554 555 switch (clk_id) { 556 case HCLK_SDMMC: 557 case SCLK_SDMMC: 558 con_id = 16; 559 break; 560 case HCLK_EMMC: 561 case SCLK_EMMC: 562 case SCLK_EMMC_SAMPLE: 563 con_id = 20; 564 break; 565 default: 566 return -EINVAL; 567 } 568 569 con = readl(&cru->clksel_con[con_id]); 570 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 571 572 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT 573 == EMMC_SEL_24M) 574 return DIV_TO_RATE(OSC_HZ, div) / 2; 575 else 576 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 577 578 } 579 580 static ulong px30_mmc_set_clk(struct px30_clk_priv *priv, 581 ulong clk_id, ulong set_rate) 582 { 583 struct px30_cru *cru = priv->cru; 584 int src_clk_div; 585 u32 con_id; 586 587 switch (clk_id) { 588 case HCLK_SDMMC: 589 case SCLK_SDMMC: 590 con_id = 16; 591 break; 592 case HCLK_EMMC: 593 case SCLK_EMMC: 594 con_id = 20; 595 break; 596 default: 597 return -EINVAL; 598 } 599 600 /* Select clk_sdmmc/emmc source from GPLL by default */ 601 /* mmc clock defaulg div 2 internal, need provide double in cru */ 602 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); 603 604 if (src_clk_div > 127) { 605 /* use 24MHz source for 400KHz clock */ 606 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 607 rk_clrsetreg(&cru->clksel_con[con_id], 608 EMMC_PLL_MASK | EMMC_DIV_MASK, 609 EMMC_SEL_24M << EMMC_PLL_SHIFT | 610 (src_clk_div - 1) << EMMC_DIV_SHIFT); 611 } else { 612 rk_clrsetreg(&cru->clksel_con[con_id], 613 EMMC_PLL_MASK | EMMC_DIV_MASK, 614 EMMC_SEL_GPLL << EMMC_PLL_SHIFT | 615 (src_clk_div - 1) << EMMC_DIV_SHIFT); 616 } 617 rk_clrsetreg(&cru->clksel_con[con_id +1], EMMC_CLK_SEL_MASK, 618 EMMC_CLK_SEL_EMMC); 619 620 return px30_mmc_get_clk(priv, clk_id); 621 } 622 623 static ulong px30_sfc_get_clk(struct px30_clk_priv *priv, uint clk_id) 624 { 625 struct px30_cru *cru = priv->cru; 626 u32 div, con; 627 628 con = readl(&cru->clksel_con[22]); 629 div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT; 630 631 return DIV_TO_RATE(priv->gpll_hz, div); 632 } 633 634 static ulong px30_sfc_set_clk(struct px30_clk_priv *priv, 635 ulong clk_id, ulong set_rate) 636 { 637 struct px30_cru *cru = priv->cru; 638 int src_clk_div; 639 640 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); 641 rk_clrsetreg(&cru->clksel_con[22], 642 SFC_PLL_SEL_MASK | SFC_DIV_CON_MASK, 643 0 << SFC_PLL_SEL_SHIFT | 644 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); 645 646 return px30_sfc_get_clk(priv, clk_id); 647 } 648 649 static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id) 650 { 651 struct px30_cru *cru = priv->cru; 652 u32 div, con; 653 654 switch (clk_id) { 655 case SCLK_PWM0: 656 con = readl(&cru->clksel_con[52]); 657 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 658 break; 659 case SCLK_PWM1: 660 con = readl(&cru->clksel_con[52]); 661 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; 662 break; 663 default: 664 printf("do not support this pwm bus\n"); 665 return -EINVAL; 666 } 667 668 return DIV_TO_RATE(priv->gpll_hz, div); 669 } 670 671 static ulong px30_pwm_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 672 { 673 struct px30_cru *cru = priv->cru; 674 int src_clk_div; 675 676 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 677 assert(src_clk_div - 1 <= 127); 678 679 switch (clk_id) { 680 case SCLK_PWM0: 681 rk_clrsetreg(&cru->clksel_con[52], 682 CLK_PWM_DIV_CON_MASK << CLK_PWM0_DIV_CON_SHIFT | 683 CLK_PWM_PLL_SEL_MASK << CLK_PWM0_PLL_SEL_SHIFT, 684 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | 685 CLK_PWM_PLL_SEL_GPLL << CLK_PWM0_PLL_SEL_SHIFT); 686 break; 687 case SCLK_PWM1: 688 rk_clrsetreg(&cru->clksel_con[52], 689 CLK_PWM_DIV_CON_MASK << CLK_PWM1_DIV_CON_SHIFT | 690 CLK_PWM_PLL_SEL_MASK << CLK_PWM1_PLL_SEL_SHIFT, 691 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | 692 CLK_PWM_PLL_SEL_GPLL << CLK_PWM1_PLL_SEL_SHIFT); 693 break; 694 default: 695 printf("do not support this pwm bus\n"); 696 return -EINVAL; 697 } 698 699 return px30_pwm_get_clk(priv, clk_id); 700 } 701 702 static ulong px30_saradc_get_clk(struct px30_clk_priv *priv) 703 { 704 struct px30_cru *cru = priv->cru; 705 u32 div, con; 706 707 con = readl(&cru->clksel_con[55]); 708 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 709 710 return DIV_TO_RATE(OSC_HZ, div); 711 } 712 713 static ulong px30_saradc_set_clk(struct px30_clk_priv *priv, uint hz) 714 { 715 struct px30_cru *cru = priv->cru; 716 int src_clk_div; 717 718 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 719 assert(src_clk_div - 1 <= 2047); 720 721 rk_clrsetreg(&cru->clksel_con[55], 722 CLK_SARADC_DIV_CON_MASK, 723 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 724 725 return px30_saradc_get_clk(priv); 726 } 727 728 static ulong px30_tsadc_get_clk(struct px30_clk_priv *priv) 729 { 730 struct px30_cru *cru = priv->cru; 731 u32 div, con; 732 733 con = readl(&cru->clksel_con[54]); 734 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; 735 736 return DIV_TO_RATE(OSC_HZ, div); 737 } 738 739 static ulong px30_tsadc_set_clk(struct px30_clk_priv *priv, uint hz) 740 { 741 struct px30_cru *cru = priv->cru; 742 int src_clk_div; 743 744 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); 745 assert(src_clk_div - 1 <= 2047); 746 747 rk_clrsetreg(&cru->clksel_con[54], 748 CLK_SARADC_DIV_CON_MASK, 749 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); 750 751 return px30_tsadc_get_clk(priv); 752 } 753 754 static ulong px30_spi_get_clk(struct px30_clk_priv *priv, ulong clk_id) 755 { 756 struct px30_cru *cru = priv->cru; 757 u32 div, con; 758 759 switch (clk_id) { 760 case SCLK_SPI0: 761 con = readl(&cru->clksel_con[53]); 762 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 763 break; 764 case SCLK_SPI1: 765 con = readl(&cru->clksel_con[53]); 766 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; 767 break; 768 default: 769 printf("do not support this pwm bus\n"); 770 return -EINVAL; 771 } 772 773 return DIV_TO_RATE(priv->gpll_hz, div); 774 } 775 776 static ulong px30_spi_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 777 { 778 struct px30_cru *cru = priv->cru; 779 int src_clk_div; 780 781 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 782 assert(src_clk_div - 1 <= 127); 783 784 switch (clk_id) { 785 case SCLK_SPI0: 786 rk_clrsetreg(&cru->clksel_con[53], 787 CLK_SPI_DIV_CON_MASK << CLK_SPI0_DIV_CON_SHIFT | 788 CLK_SPI_PLL_SEL_MASK << CLK_SPI0_PLL_SEL_SHIFT, 789 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | 790 CLK_SPI_PLL_SEL_GPLL << CLK_SPI0_PLL_SEL_SHIFT); 791 break; 792 case SCLK_SPI1: 793 rk_clrsetreg(&cru->clksel_con[53], 794 CLK_SPI_DIV_CON_MASK << CLK_SPI1_DIV_CON_SHIFT | 795 CLK_SPI_PLL_SEL_MASK << CLK_SPI1_PLL_SEL_SHIFT, 796 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | 797 CLK_SPI_PLL_SEL_GPLL << CLK_SPI1_PLL_SEL_SHIFT); 798 break; 799 default: 800 printf("do not support this pwm bus\n"); 801 return -EINVAL; 802 } 803 804 return px30_spi_get_clk(priv, clk_id); 805 } 806 807 static ulong px30_vop_get_clk(struct px30_clk_priv *priv, ulong clk_id) 808 { 809 struct px30_cru *cru = priv->cru; 810 u32 div, con, parent; 811 812 switch (clk_id) { 813 case ACLK_VOPB: 814 case ACLK_VOPL: 815 con = readl(&cru->clksel_con[3]); 816 div = con & ACLK_VO_DIV_MASK; 817 parent = priv->gpll_hz; 818 break; 819 case DCLK_VOPB: 820 con = readl(&cru->clksel_con[5]); 821 div = con & DCLK_VOPB_DIV_MASK; 822 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); 823 break; 824 case DCLK_VOPL: 825 con = readl(&cru->clksel_con[8]); 826 div = con & DCLK_VOPL_DIV_MASK; 827 parent = rkclk_pll_get_rate(&cru->pll[NPLL], &cru->mode, NPLL); 828 break; 829 default: 830 return -ENOENT; 831 } 832 833 return DIV_TO_RATE(parent, div); 834 } 835 836 static ulong px30_vop_set_clk(struct px30_clk_priv *priv, ulong clk_id, uint hz) 837 { 838 struct px30_cru *cru = priv->cru; 839 ulong npll_hz; 840 int src_clk_div; 841 842 switch (clk_id) { 843 case ACLK_VOPB: 844 case ACLK_VOPL: 845 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 846 assert(src_clk_div - 1 <= 31); 847 rk_clrsetreg(&cru->clksel_con[3], 848 ACLK_VO_PLL_MASK | ACLK_VO_DIV_MASK, 849 ACLK_VO_SEL_GPLL << ACLK_VO_PLL_SHIFT | 850 (src_clk_div - 1) << ACLK_VO_DIV_SHIFT); 851 break; 852 case DCLK_VOPB: 853 if (hz < PX30_VOP_PLL_LIMIT) { 854 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 855 if (src_clk_div % 2) 856 src_clk_div = src_clk_div - 1; 857 } else { 858 src_clk_div = 1; 859 } 860 assert(src_clk_div - 1 <= 255); 861 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); 862 rk_clrsetreg(&cru->clksel_con[5], 863 DCLK_VOPB_SEL_MASK | DCLK_VOPB_PLL_SEL_MASK | 864 DCLK_VOPB_DIV_MASK, 865 DCLK_VOPB_SEL_DIVOUT << DCLK_VOPB_SEL_SHIFT | 866 DCLK_VOPB_PLL_SEL_CPLL << DCLK_VOPB_PLL_SEL_SHIFT | 867 (src_clk_div - 1) << DCLK_VOPB_DIV_SHIFT); 868 break; 869 case DCLK_VOPL: 870 npll_hz = px30_clk_get_pll_rate(priv, NPLL); 871 if (npll_hz >= PX30_VOP_PLL_LIMIT && npll_hz >= hz && npll_hz % hz == 0) { 872 src_clk_div = npll_hz / hz; 873 assert(src_clk_div - 1 <= 255); 874 } else { 875 if (hz < PX30_VOP_PLL_LIMIT) { 876 src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz); 877 if (src_clk_div % 2) 878 src_clk_div = src_clk_div - 1; 879 } else { 880 src_clk_div = 1; 881 } 882 assert(src_clk_div - 1 <= 255); 883 rkclk_set_pll(&cru->pll[NPLL], &cru->mode, NPLL, hz * src_clk_div); 884 } 885 rk_clrsetreg(&cru->clksel_con[8], 886 DCLK_VOPL_SEL_MASK | DCLK_VOPL_PLL_SEL_MASK | 887 DCLK_VOPL_DIV_MASK, 888 DCLK_VOPL_SEL_DIVOUT << DCLK_VOPL_SEL_SHIFT | 889 DCLK_VOPL_PLL_SEL_NPLL << DCLK_VOPL_PLL_SEL_SHIFT | 890 (src_clk_div - 1) << DCLK_VOPL_DIV_SHIFT); 891 break; 892 default: 893 printf("do not support this vop freq\n"); 894 return -EINVAL; 895 } 896 897 return px30_vop_get_clk(priv, clk_id); 898 } 899 900 static ulong px30_bus_get_clk(struct px30_clk_priv *priv, ulong clk_id) 901 { 902 struct px30_cru *cru = priv->cru; 903 u32 div, con, parent; 904 905 switch (clk_id) { 906 case ACLK_BUS_PRE: 907 con = readl(&cru->clksel_con[23]); 908 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; 909 parent = priv->gpll_hz; 910 break; 911 case HCLK_BUS_PRE: 912 con = readl(&cru->clksel_con[24]); 913 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; 914 parent = priv->gpll_hz; 915 break; 916 case PCLK_BUS_PRE: 917 case PCLK_WDT_NS: 918 parent = px30_bus_get_clk(priv, ACLK_BUS_PRE); 919 con = readl(&cru->clksel_con[24]); 920 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; 921 break; 922 default: 923 return -ENOENT; 924 } 925 926 return DIV_TO_RATE(parent, div); 927 } 928 929 static ulong px30_bus_set_clk(struct px30_clk_priv *priv, ulong clk_id, 930 ulong hz) 931 { 932 struct px30_cru *cru = priv->cru; 933 int src_clk_div; 934 935 /* 936 * select gpll as pd_bus bus clock source and 937 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 938 */ 939 switch (clk_id) { 940 case ACLK_BUS_PRE: 941 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 942 assert(src_clk_div - 1 <= 31); 943 rk_clrsetreg(&cru->clksel_con[23], 944 BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 945 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 946 (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT); 947 break; 948 case HCLK_BUS_PRE: 949 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 950 assert(src_clk_div - 1 <= 31); 951 rk_clrsetreg(&cru->clksel_con[24], 952 BUS_PLL_SEL_MASK | BUS_HCLK_DIV_MASK, 953 BUS_PLL_SEL_GPLL << BUS_PLL_SEL_SHIFT | 954 (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT); 955 break; 956 case PCLK_BUS_PRE: 957 src_clk_div = 958 DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz); 959 assert(src_clk_div - 1 <= 3); 960 rk_clrsetreg(&cru->clksel_con[24], 961 BUS_PCLK_DIV_MASK, 962 (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT); 963 break; 964 default: 965 printf("do not support this bus freq\n"); 966 return -EINVAL; 967 } 968 969 return px30_bus_get_clk(priv, clk_id); 970 } 971 972 static ulong px30_peri_get_clk(struct px30_clk_priv *priv, ulong clk_id) 973 { 974 struct px30_cru *cru = priv->cru; 975 u32 div, con, parent; 976 977 switch (clk_id) { 978 case ACLK_PERI_PRE: 979 con = readl(&cru->clksel_con[14]); 980 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; 981 parent = priv->gpll_hz; 982 break; 983 case HCLK_PERI_PRE: 984 con = readl(&cru->clksel_con[14]); 985 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; 986 parent = priv->gpll_hz; 987 break; 988 default: 989 return -ENOENT; 990 } 991 992 return DIV_TO_RATE(parent, div); 993 } 994 995 static ulong px30_peri_set_clk(struct px30_clk_priv *priv, ulong clk_id, 996 ulong hz) 997 { 998 struct px30_cru *cru = priv->cru; 999 int src_clk_div; 1000 1001 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1002 assert(src_clk_div - 1 <= 31); 1003 1004 /* 1005 * select gpll as pd_peri bus clock source and 1006 * set up dependent divisors for HCLK and ACLK clocks. 1007 */ 1008 switch (clk_id) { 1009 case ACLK_PERI_PRE: 1010 rk_clrsetreg(&cru->clksel_con[14], 1011 PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK, 1012 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 1013 (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT); 1014 break; 1015 case HCLK_PERI_PRE: 1016 rk_clrsetreg(&cru->clksel_con[14], 1017 PERI_PLL_SEL_MASK | PERI_HCLK_DIV_MASK, 1018 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 1019 (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT); 1020 break; 1021 default: 1022 printf("do not support this peri freq\n"); 1023 return -EINVAL; 1024 } 1025 1026 return px30_peri_get_clk(priv, clk_id); 1027 } 1028 1029 #ifndef CONFIG_SPL_BUILD 1030 static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id) 1031 { 1032 struct px30_cru *cru = priv->cru; 1033 u32 div, con, parent; 1034 1035 switch (clk_id) { 1036 case SCLK_CRYPTO: 1037 con = readl(&cru->clksel_con[25]); 1038 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; 1039 parent = priv->gpll_hz; 1040 break; 1041 case SCLK_CRYPTO_APK: 1042 con = readl(&cru->clksel_con[25]); 1043 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; 1044 parent = priv->gpll_hz; 1045 break; 1046 default: 1047 return -ENOENT; 1048 } 1049 1050 return DIV_TO_RATE(parent, div); 1051 } 1052 1053 static ulong px30_crypto_set_clk(struct px30_clk_priv *priv, ulong clk_id, 1054 ulong hz) 1055 { 1056 struct px30_cru *cru = priv->cru; 1057 int src_clk_div; 1058 1059 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1060 assert(src_clk_div - 1 <= 31); 1061 1062 /* 1063 * select gpll as crypto clock source and 1064 * set up dependent divisors for crypto clocks. 1065 */ 1066 switch (clk_id) { 1067 case SCLK_CRYPTO: 1068 rk_clrsetreg(&cru->clksel_con[25], 1069 CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK, 1070 CRYPTO_PLL_SEL_GPLL << CRYPTO_PLL_SEL_SHIFT | 1071 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); 1072 break; 1073 case SCLK_CRYPTO_APK: 1074 rk_clrsetreg(&cru->clksel_con[25], 1075 CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK, 1076 CRYPTO_PLL_SEL_GPLL << CRYPTO_APK_SEL_SHIFT | 1077 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); 1078 break; 1079 default: 1080 printf("do not support this peri freq\n"); 1081 return -EINVAL; 1082 } 1083 1084 return px30_crypto_get_clk(priv, clk_id); 1085 } 1086 1087 static ulong px30_mac_set_clk(struct clk *clk, uint hz) 1088 { 1089 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1090 struct px30_cru *cru = priv->cru; 1091 u32 con = readl(&cru->clksel_con[22]); 1092 ulong pll_rate; 1093 u8 div; 1094 1095 if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_CPLL) 1096 pll_rate = px30_clk_get_pll_rate(priv, CPLL); 1097 else if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_NPLL) 1098 pll_rate = px30_clk_get_pll_rate(priv, NPLL); 1099 else 1100 pll_rate = priv->gpll_hz; 1101 1102 /*default set 50MHZ for gmac*/ 1103 if (!hz) 1104 hz = 50000000; 1105 1106 div = DIV_ROUND_UP(pll_rate, hz) - 1; 1107 assert(div < 32); 1108 rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK, 1109 div << CLK_GMAC_DIV_SHIFT); 1110 1111 return DIV_TO_RATE(pll_rate, div); 1112 } 1113 1114 static int px30_mac_set_speed_clk(struct clk *clk, uint hz) 1115 { 1116 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1117 struct px30_cru *cru = priv->cru; 1118 1119 if (hz != 2500000 && hz != 25000000) { 1120 debug("Unsupported mac speed:%d\n", hz); 1121 return -EINVAL; 1122 } 1123 1124 rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK, 1125 ((hz == 2500000) ? 0 : 1) << RMII_CLK_SEL_SHIFT); 1126 1127 return 0; 1128 } 1129 1130 #endif 1131 1132 static int px30_clk_get_gpll_rate(ulong *rate) 1133 { 1134 struct udevice *pmucru_dev; 1135 struct px30_pmuclk_priv *priv; 1136 int ret; 1137 1138 ret = uclass_get_device_by_driver(UCLASS_CLK, 1139 DM_GET_DRIVER(rockchip_px30_pmucru), 1140 &pmucru_dev); 1141 if (ret) { 1142 printf("%s: could not find pmucru device\n", __func__); 1143 return ret; 1144 } 1145 priv = dev_get_priv(pmucru_dev); 1146 *rate = priv->gpll_hz; 1147 1148 return 0; 1149 } 1150 1151 static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv, 1152 enum px30_pll_id pll_id) 1153 { 1154 struct px30_cru *cru = priv->cru; 1155 1156 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1157 } 1158 1159 static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv, 1160 enum px30_pll_id pll_id, ulong hz) 1161 { 1162 struct px30_cru *cru = priv->cru; 1163 1164 if (rkclk_set_pll(&cru->pll[pll_id], &cru->mode, pll_id, hz)) 1165 return -EINVAL; 1166 return rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id); 1167 } 1168 1169 static ulong px30_armclk_set_clk(struct px30_clk_priv *priv, ulong hz) 1170 { 1171 struct px30_cru *cru = priv->cru; 1172 const struct cpu_rate_table *rate; 1173 ulong old_rate; 1174 1175 rate = get_cpu_settings(hz); 1176 if (!rate) { 1177 printf("%s unsupport rate\n", __func__); 1178 return -EINVAL; 1179 } 1180 1181 /* 1182 * select apll as cpu/core clock pll source and 1183 * set up dependent divisors for PERI and ACLK clocks. 1184 * core hz : apll = 1:1 1185 */ 1186 old_rate = px30_clk_get_pll_rate(priv, APLL); 1187 if (old_rate > hz) { 1188 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1189 return -EINVAL; 1190 rk_clrsetreg(&cru->clksel_con[0], 1191 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1192 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1193 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1194 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1195 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1196 0 << CORE_DIV_CON_SHIFT); 1197 } else if (old_rate < hz) { 1198 rk_clrsetreg(&cru->clksel_con[0], 1199 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK | 1200 CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK, 1201 rate->aclk_div << CORE_ACLK_DIV_SHIFT | 1202 rate->pclk_div << CORE_DBG_DIV_SHIFT | 1203 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 1204 0 << CORE_DIV_CON_SHIFT); 1205 if (rkclk_set_pll(&cru->pll[APLL], &cru->mode, APLL, hz)) 1206 return -EINVAL; 1207 } 1208 1209 return px30_clk_get_pll_rate(priv, APLL); 1210 } 1211 1212 static ulong px30_clk_get_rate(struct clk *clk) 1213 { 1214 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1215 ulong rate = 0; 1216 1217 if (!priv->gpll_hz && clk->id > ARMCLK) { 1218 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1219 return -ENOENT; 1220 } 1221 1222 debug("%s %ld\n", __func__, clk->id); 1223 switch (clk->id) { 1224 case PLL_APLL: 1225 rate = px30_clk_get_pll_rate(priv, APLL); 1226 break; 1227 case PLL_DPLL: 1228 rate = px30_clk_get_pll_rate(priv, DPLL); 1229 break; 1230 case PLL_CPLL: 1231 rate = px30_clk_get_pll_rate(priv, CPLL); 1232 break; 1233 case PLL_NPLL: 1234 rate = px30_clk_get_pll_rate(priv, NPLL); 1235 break; 1236 case ARMCLK: 1237 rate = px30_clk_get_pll_rate(priv, APLL); 1238 break; 1239 case HCLK_SDMMC: 1240 case HCLK_EMMC: 1241 case SCLK_SDMMC: 1242 case SCLK_EMMC: 1243 case SCLK_EMMC_SAMPLE: 1244 rate = px30_mmc_get_clk(priv, clk->id); 1245 break; 1246 case SCLK_SFC: 1247 rate = px30_sfc_get_clk(priv, clk->id); 1248 break; 1249 case SCLK_I2C0: 1250 case SCLK_I2C1: 1251 case SCLK_I2C2: 1252 case SCLK_I2C3: 1253 rate = px30_i2c_get_clk(priv, clk->id); 1254 break; 1255 case SCLK_I2S1: 1256 rate = px30_i2s_get_clk(priv, clk->id); 1257 break; 1258 case SCLK_I2S1_OUT: 1259 rate = px30_i2s1_mclk_get_clk(priv, clk->id); 1260 break; 1261 case SCLK_PWM0: 1262 case SCLK_PWM1: 1263 rate = px30_pwm_get_clk(priv, clk->id); 1264 break; 1265 case SCLK_SARADC: 1266 rate = px30_saradc_get_clk(priv); 1267 break; 1268 case SCLK_TSADC: 1269 rate = px30_tsadc_get_clk(priv); 1270 break; 1271 case SCLK_SPI0: 1272 case SCLK_SPI1: 1273 rate = px30_spi_get_clk(priv, clk->id); 1274 break; 1275 case ACLK_VOPB: 1276 case ACLK_VOPL: 1277 case DCLK_VOPB: 1278 case DCLK_VOPL: 1279 rate = px30_vop_get_clk(priv, clk->id); 1280 break; 1281 case ACLK_BUS_PRE: 1282 case HCLK_BUS_PRE: 1283 case PCLK_BUS_PRE: 1284 case PCLK_WDT_NS: 1285 rate = px30_bus_get_clk(priv, clk->id); 1286 break; 1287 case ACLK_PERI_PRE: 1288 case HCLK_PERI_PRE: 1289 rate = px30_peri_get_clk(priv, clk->id); 1290 break; 1291 #ifndef CONFIG_SPL_BUILD 1292 case SCLK_CRYPTO: 1293 case SCLK_CRYPTO_APK: 1294 rate = px30_crypto_get_clk(priv, clk->id); 1295 break; 1296 #endif 1297 default: 1298 return -ENOENT; 1299 } 1300 1301 return rate; 1302 } 1303 1304 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) 1305 { 1306 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1307 ulong ret = 0; 1308 1309 if (!priv->gpll_hz && clk->id > ARMCLK) { 1310 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1311 return -ENOENT; 1312 } 1313 1314 debug("%s %ld %ld\n", __func__, clk->id, rate); 1315 switch (clk->id) { 1316 case PLL_NPLL: 1317 ret = px30_clk_set_pll_rate(priv, NPLL, rate); 1318 break; 1319 case ARMCLK: 1320 if (priv->armclk_hz) 1321 px30_armclk_set_clk(priv, rate); 1322 priv->armclk_hz = rate; 1323 break; 1324 case HCLK_SDMMC: 1325 case HCLK_EMMC: 1326 case SCLK_SDMMC: 1327 case SCLK_EMMC: 1328 ret = px30_mmc_set_clk(priv, clk->id, rate); 1329 break; 1330 case SCLK_SFC: 1331 ret = px30_sfc_set_clk(priv, clk->id, rate); 1332 break; 1333 case SCLK_I2C0: 1334 case SCLK_I2C1: 1335 case SCLK_I2C2: 1336 case SCLK_I2C3: 1337 ret = px30_i2c_set_clk(priv, clk->id, rate); 1338 break; 1339 case SCLK_I2S1: 1340 ret = px30_i2s_set_clk(priv, clk->id, rate); 1341 break; 1342 case SCLK_I2S1_OUT: 1343 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate); 1344 break; 1345 case SCLK_PWM0: 1346 case SCLK_PWM1: 1347 ret = px30_pwm_set_clk(priv, clk->id, rate); 1348 break; 1349 case SCLK_SARADC: 1350 ret = px30_saradc_set_clk(priv, rate); 1351 break; 1352 case SCLK_TSADC: 1353 ret = px30_tsadc_set_clk(priv, rate); 1354 break; 1355 case SCLK_SPI0: 1356 case SCLK_SPI1: 1357 ret = px30_spi_set_clk(priv, clk->id, rate); 1358 break; 1359 case ACLK_VOPB: 1360 case ACLK_VOPL: 1361 case DCLK_VOPB: 1362 case DCLK_VOPL: 1363 ret = px30_vop_set_clk(priv, clk->id, rate); 1364 break; 1365 case ACLK_BUS_PRE: 1366 case HCLK_BUS_PRE: 1367 case PCLK_BUS_PRE: 1368 ret = px30_bus_set_clk(priv, clk->id, rate); 1369 break; 1370 case ACLK_PERI_PRE: 1371 case HCLK_PERI_PRE: 1372 ret = px30_peri_set_clk(priv, clk->id, rate); 1373 break; 1374 #ifndef CONFIG_SPL_BUILD 1375 case SCLK_CRYPTO: 1376 case SCLK_CRYPTO_APK: 1377 ret = px30_crypto_set_clk(priv, clk->id, rate); 1378 break; 1379 case SCLK_GMAC: 1380 case SCLK_GMAC_SRC: 1381 ret = px30_mac_set_clk(clk, rate); 1382 break; 1383 case SCLK_GMAC_RMII: 1384 ret = px30_mac_set_speed_clk(clk, rate); 1385 break; 1386 #endif 1387 default: 1388 return -ENOENT; 1389 } 1390 1391 return ret; 1392 } 1393 1394 #define ROCKCHIP_MMC_DELAY_SEL BIT(10) 1395 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1396 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 1397 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1398 1399 #define PSECS_PER_SEC 1000000000000LL 1400 /* 1401 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1402 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1403 */ 1404 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1405 1406 int rockchip_mmc_get_phase(struct clk *clk) 1407 { 1408 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1409 struct px30_cru *cru = priv->cru; 1410 u32 raw_value, delay_num; 1411 u16 degrees = 0; 1412 ulong rate; 1413 1414 rate = px30_clk_get_rate(clk); 1415 1416 if (rate < 0) 1417 return rate; 1418 1419 if (clk->id == SCLK_EMMC_SAMPLE) 1420 raw_value = readl(&cru->emmc_con[1]); 1421 else 1422 raw_value = readl(&cru->sdmmc_con[1]); 1423 1424 raw_value >>= 1; 1425 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1426 1427 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1428 /* degrees/delaynum * 10000 */ 1429 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1430 36 * (rate / 1000000); 1431 1432 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1433 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1434 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1435 } 1436 1437 return degrees % 360; 1438 } 1439 1440 int rockchip_mmc_set_phase(struct clk *clk, u32 degrees) 1441 { 1442 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1443 struct px30_cru *cru = priv->cru; 1444 u8 nineties, remainder, delay_num; 1445 u32 raw_value, delay; 1446 ulong rate; 1447 1448 rate = px30_clk_get_rate(clk); 1449 1450 if (rate < 0) 1451 return rate; 1452 1453 nineties = degrees / 90; 1454 remainder = (degrees % 90); 1455 1456 /* 1457 * Convert to delay; do a little extra work to make sure we 1458 * don't overflow 32-bit / 64-bit numbers. 1459 */ 1460 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1461 delay *= remainder; 1462 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1463 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1464 1465 delay_num = (u8)min_t(u32, delay, 255); 1466 1467 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1468 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1469 raw_value |= nineties; 1470 1471 raw_value <<= 1; 1472 if (clk->id == SCLK_EMMC_SAMPLE) 1473 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); 1474 else 1475 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); 1476 1477 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1478 degrees, delay_num, raw_value, rockchip_mmc_get_phase(clk)); 1479 1480 return 0; 1481 } 1482 1483 static int px30_clk_get_phase(struct clk *clk) 1484 { 1485 int ret; 1486 1487 debug("%s %ld\n", __func__, clk->id); 1488 switch (clk->id) { 1489 case SCLK_EMMC_SAMPLE: 1490 case SCLK_SDMMC_SAMPLE: 1491 ret = rockchip_mmc_get_phase(clk); 1492 break; 1493 default: 1494 return -ENOENT; 1495 } 1496 1497 return ret; 1498 } 1499 1500 static int px30_clk_set_phase(struct clk *clk, int degrees) 1501 { 1502 int ret; 1503 1504 debug("%s %ld\n", __func__, clk->id); 1505 switch (clk->id) { 1506 case SCLK_EMMC_SAMPLE: 1507 case SCLK_SDMMC_SAMPLE: 1508 ret = rockchip_mmc_set_phase(clk, degrees); 1509 break; 1510 default: 1511 return -ENOENT; 1512 } 1513 1514 return ret; 1515 } 1516 1517 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1518 static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) 1519 { 1520 struct px30_clk_priv *priv = dev_get_priv(clk->dev); 1521 struct px30_cru *cru = priv->cru; 1522 1523 if (parent->id == SCLK_GMAC_SRC) { 1524 debug("%s: switching GAMC to SCLK_GMAC_SRC\n", __func__); 1525 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, 1526 RMII_EXTCLK_SEL_INT << RMII_EXTCLK_SEL_SHIFT); 1527 } else { 1528 debug("%s: switching GMAC to external clock\n", __func__); 1529 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, 1530 RMII_EXTCLK_SEL_EXT << RMII_EXTCLK_SEL_SHIFT); 1531 } 1532 return 0; 1533 } 1534 1535 static int px30_clk_set_parent(struct clk *clk, struct clk *parent) 1536 { 1537 switch (clk->id) { 1538 case SCLK_GMAC: 1539 return px30_gmac_set_parent(clk, parent); 1540 default: 1541 return -ENOENT; 1542 } 1543 } 1544 #endif 1545 1546 static struct clk_ops px30_clk_ops = { 1547 .get_rate = px30_clk_get_rate, 1548 .set_rate = px30_clk_set_rate, 1549 .get_phase = px30_clk_get_phase, 1550 .set_phase = px30_clk_set_phase, 1551 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1552 .set_parent = px30_clk_set_parent, 1553 #endif 1554 }; 1555 1556 static int px30_clk_probe(struct udevice *dev) 1557 { 1558 struct px30_clk_priv *priv = dev_get_priv(dev); 1559 int ret; 1560 1561 priv->sync_kernel = false; 1562 if (!priv->armclk_enter_hz) { 1563 priv->armclk_enter_hz = px30_clk_get_pll_rate(priv, APLL); 1564 priv->armclk_init_hz = priv->armclk_enter_hz; 1565 } 1566 if (px30_clk_get_pll_rate(priv, APLL) != APLL_HZ) { 1567 ret = px30_armclk_set_clk(priv, APLL_HZ); 1568 if (ret < 0) 1569 printf("%s failed to set armclk rate\n", __func__); 1570 priv->armclk_init_hz = APLL_HZ; 1571 } 1572 1573 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1574 ret = clk_set_defaults(dev); 1575 if (ret) 1576 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1577 else 1578 priv->sync_kernel = true; 1579 1580 if (!priv->gpll_hz) { 1581 ret = px30_clk_get_gpll_rate(&priv->gpll_hz); 1582 if (ret) { 1583 printf("%s failed to get gpll rate\n", __func__); 1584 return ret; 1585 } 1586 } 1587 1588 return 0; 1589 } 1590 1591 static int px30_clk_ofdata_to_platdata(struct udevice *dev) 1592 { 1593 struct px30_clk_priv *priv = dev_get_priv(dev); 1594 1595 priv->cru = dev_read_addr_ptr(dev); 1596 1597 return 0; 1598 } 1599 1600 static int px30_clk_bind(struct udevice *dev) 1601 { 1602 int ret; 1603 struct udevice *sys_child, *sf_child; 1604 struct sysreset_reg *priv; 1605 struct softreset_reg *sf_priv; 1606 1607 /* The reset driver does not have a device node, so bind it here */ 1608 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1609 &sys_child); 1610 if (ret) { 1611 debug("Warning: No sysreset driver: ret=%d\n", ret); 1612 } else { 1613 priv = malloc(sizeof(struct sysreset_reg)); 1614 priv->glb_srst_fst_value = offsetof(struct px30_cru, 1615 glb_srst_fst); 1616 priv->glb_srst_snd_value = offsetof(struct px30_cru, 1617 glb_srst_snd); 1618 sys_child->priv = priv; 1619 } 1620 1621 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1622 dev_ofnode(dev), &sf_child); 1623 if (ret) { 1624 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1625 } else { 1626 sf_priv = malloc(sizeof(struct softreset_reg)); 1627 sf_priv->sf_reset_offset = offsetof(struct px30_cru, 1628 softrst_con[0]); 1629 sf_priv->sf_reset_num = 12; 1630 sf_child->priv = sf_priv; 1631 } 1632 1633 return 0; 1634 } 1635 1636 static const struct udevice_id px30_clk_ids[] = { 1637 { .compatible = "rockchip,px30-cru" }, 1638 { } 1639 }; 1640 1641 U_BOOT_DRIVER(rockchip_px30_cru) = { 1642 .name = "rockchip_px30_cru", 1643 .id = UCLASS_CLK, 1644 .of_match = px30_clk_ids, 1645 .priv_auto_alloc_size = sizeof(struct px30_clk_priv), 1646 .ofdata_to_platdata = px30_clk_ofdata_to_platdata, 1647 .ops = &px30_clk_ops, 1648 .bind = px30_clk_bind, 1649 .probe = px30_clk_probe, 1650 }; 1651 1652 static ulong px30_pclk_pmu_get_pmuclk(struct px30_pmuclk_priv *priv) 1653 { 1654 struct px30_pmucru *pmucru = priv->pmucru; 1655 u32 div, con; 1656 1657 con = readl(&pmucru->pmu_clksel_con[0]); 1658 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; 1659 1660 return DIV_TO_RATE(priv->gpll_hz, div); 1661 } 1662 1663 static ulong px30_pclk_pmu_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1664 { 1665 struct px30_pmucru *pmucru = priv->pmucru; 1666 int src_clk_div; 1667 1668 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); 1669 assert(src_clk_div - 1 <= 31); 1670 1671 rk_clrsetreg(&pmucru->pmu_clksel_con[0], 1672 CLK_PMU_PCLK_DIV_MASK, 1673 (src_clk_div - 1) << CLK_PMU_PCLK_DIV_SHIFT); 1674 1675 return px30_pclk_pmu_get_pmuclk(priv); 1676 } 1677 1678 static ulong px30_gpll_get_pmuclk(struct px30_pmuclk_priv *priv) 1679 { 1680 struct px30_pmucru *pmucru = priv->pmucru; 1681 1682 return rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL); 1683 } 1684 1685 static ulong px30_gpll_set_pmuclk(struct px30_pmuclk_priv *priv, ulong hz) 1686 { 1687 struct udevice *cru_dev; 1688 struct px30_clk_priv *cru_priv; 1689 struct px30_pmucru *pmucru = priv->pmucru; 1690 u32 div; 1691 ulong emmc_rate, sdmmc_rate, nandc_rate, sfc_rate; 1692 ulong aclk_bus_rate, hclk_bus_rate, pclk_bus_rate; 1693 ulong aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate; 1694 int ret; 1695 1696 ret = uclass_get_device_by_name(UCLASS_CLK, 1697 "clock-controller@ff2b0000", 1698 &cru_dev); 1699 if (ret) { 1700 printf("%s failed to get cru device\n", __func__); 1701 return ret; 1702 } 1703 cru_priv = dev_get_priv(cru_dev); 1704 1705 if (priv->gpll_hz == hz) 1706 return priv->gpll_hz; 1707 1708 cru_priv->gpll_hz = priv->gpll_hz; 1709 div = DIV_ROUND_UP(hz, priv->gpll_hz); 1710 1711 /* save clock rate */ 1712 aclk_bus_rate = px30_bus_get_clk(cru_priv, ACLK_BUS_PRE); 1713 hclk_bus_rate = px30_bus_get_clk(cru_priv, HCLK_BUS_PRE); 1714 pclk_bus_rate = px30_bus_get_clk(cru_priv, PCLK_BUS_PRE); 1715 aclk_peri_rate = px30_peri_get_clk(cru_priv, ACLK_PERI_PRE); 1716 hclk_peri_rate = px30_peri_get_clk(cru_priv, HCLK_PERI_PRE); 1717 pclk_pmu_rate = px30_pclk_pmu_get_pmuclk(priv); 1718 debug("%s aclk_bus=%lu, hclk_bus=%lu, pclk_bus=%lu\n", __func__, 1719 aclk_bus_rate, hclk_bus_rate, pclk_bus_rate); 1720 debug("%s aclk_peri=%lu, hclk_peri=%lu, pclk_pmu=%lu\n", __func__, 1721 aclk_peri_rate, hclk_peri_rate, pclk_pmu_rate); 1722 emmc_rate = px30_mmc_get_clk(cru_priv, SCLK_EMMC); 1723 sdmmc_rate = px30_mmc_get_clk(cru_priv, SCLK_SDMMC); 1724 nandc_rate = px30_nandc_get_clk(cru_priv); 1725 sfc_rate = px30_sfc_get_clk(cru_priv, SCLK_SFC); 1726 debug("%s emmc=%lu, sdmmc=%lu, nandc=%lu sfc=%lu\n", __func__, 1727 emmc_rate, sdmmc_rate, nandc_rate, sfc_rate); 1728 1729 /* avoid rate too large, reduce rate first */ 1730 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate / div); 1731 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate / div); 1732 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate / div); 1733 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate / div); 1734 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate / div); 1735 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate / div); 1736 1737 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate / div); 1738 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate / div); 1739 px30_nandc_set_clk(cru_priv, nandc_rate / div); 1740 px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate / div); 1741 1742 /* change gpll rate */ 1743 rkclk_set_pll(&pmucru->pll, &pmucru->pmu_mode, GPLL, hz); 1744 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1745 cru_priv->gpll_hz = priv->gpll_hz; 1746 1747 /* restore clock rate */ 1748 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, aclk_bus_rate); 1749 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, hclk_bus_rate); 1750 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, pclk_bus_rate); 1751 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, aclk_peri_rate); 1752 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, hclk_peri_rate); 1753 px30_pclk_pmu_set_pmuclk(priv, pclk_pmu_rate); 1754 1755 px30_mmc_set_clk(cru_priv, SCLK_EMMC, emmc_rate); 1756 px30_mmc_set_clk(cru_priv, SCLK_SDMMC, sdmmc_rate); 1757 px30_nandc_set_clk(cru_priv, nandc_rate); 1758 px30_sfc_set_clk(cru_priv, SCLK_SFC, sfc_rate); 1759 1760 return priv->gpll_hz; 1761 } 1762 1763 static ulong px30_pmuclk_get_rate(struct clk *clk) 1764 { 1765 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1766 ulong rate = 0; 1767 1768 debug("%s %ld\n", __func__, clk->id); 1769 switch (clk->id) { 1770 case PLL_GPLL: 1771 rate = px30_gpll_get_pmuclk(priv); 1772 break; 1773 case PCLK_PMU_PRE: 1774 rate = px30_pclk_pmu_get_pmuclk(priv); 1775 break; 1776 default: 1777 return -ENOENT; 1778 } 1779 1780 return rate; 1781 } 1782 1783 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) 1784 { 1785 struct px30_pmuclk_priv *priv = dev_get_priv(clk->dev); 1786 ulong ret = 0; 1787 1788 debug("%s %ld %ld\n", __func__, clk->id, rate); 1789 switch (clk->id) { 1790 case PLL_GPLL: 1791 ret = px30_gpll_set_pmuclk(priv, rate); 1792 break; 1793 case PCLK_PMU_PRE: 1794 ret = px30_pclk_pmu_set_pmuclk(priv, rate); 1795 break; 1796 default: 1797 return -ENOENT; 1798 } 1799 1800 return ret; 1801 } 1802 1803 static struct clk_ops px30_pmuclk_ops = { 1804 .get_rate = px30_pmuclk_get_rate, 1805 .set_rate = px30_pmuclk_set_rate, 1806 }; 1807 1808 static void px30_clk_init(struct px30_pmuclk_priv *priv) 1809 { 1810 struct udevice *cru_dev; 1811 struct px30_clk_priv *cru_priv; 1812 ulong npll_hz; 1813 int ret; 1814 1815 priv->gpll_hz = px30_gpll_get_pmuclk(priv); 1816 if (priv->gpll_hz != GPLL_HZ) { 1817 ret = px30_gpll_set_pmuclk(priv, GPLL_HZ); 1818 if (ret < 0) 1819 printf("%s failed to set gpll rate\n", __func__); 1820 } 1821 1822 ret = uclass_get_device_by_name(UCLASS_CLK, 1823 "clock-controller@ff2b0000", 1824 &cru_dev); 1825 if (ret) { 1826 printf("%s failed to get cru device\n", __func__); 1827 return; 1828 } 1829 cru_priv = dev_get_priv(cru_dev); 1830 cru_priv->gpll_hz = priv->gpll_hz; 1831 1832 npll_hz = px30_clk_get_pll_rate(cru_priv, NPLL); 1833 if (npll_hz != NPLL_HZ) { 1834 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); 1835 if (ret < 0) 1836 printf("%s failed to set npll rate\n", __func__); 1837 } 1838 1839 px30_bus_set_clk(cru_priv, ACLK_BUS_PRE, ACLK_BUS_HZ); 1840 px30_bus_set_clk(cru_priv, HCLK_BUS_PRE, HCLK_BUS_HZ); 1841 px30_bus_set_clk(cru_priv, PCLK_BUS_PRE, PCLK_BUS_HZ); 1842 px30_peri_set_clk(cru_priv, ACLK_PERI_PRE, ACLK_PERI_HZ); 1843 px30_peri_set_clk(cru_priv, HCLK_PERI_PRE, HCLK_PERI_HZ); 1844 px30_pclk_pmu_set_pmuclk(priv, PCLK_PMU_HZ); 1845 } 1846 1847 static int px30_pmuclk_probe(struct udevice *dev) 1848 { 1849 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1850 int ret; 1851 1852 px30_clk_init(priv); 1853 1854 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1855 ret = clk_set_defaults(dev); 1856 if (ret) 1857 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1858 1859 return 0; 1860 } 1861 1862 static int px30_pmuclk_ofdata_to_platdata(struct udevice *dev) 1863 { 1864 struct px30_pmuclk_priv *priv = dev_get_priv(dev); 1865 1866 priv->pmucru = dev_read_addr_ptr(dev); 1867 1868 return 0; 1869 } 1870 1871 static const struct udevice_id px30_pmuclk_ids[] = { 1872 { .compatible = "rockchip,px30-pmucru" }, 1873 { } 1874 }; 1875 1876 U_BOOT_DRIVER(rockchip_px30_pmucru) = { 1877 .name = "rockchip_px30_pmucru", 1878 .id = UCLASS_CLK, 1879 .of_match = px30_pmuclk_ids, 1880 .priv_auto_alloc_size = sizeof(struct px30_pmuclk_priv), 1881 .ofdata_to_platdata = px30_pmuclk_ofdata_to_platdata, 1882 .ops = &px30_pmuclk_ops, 1883 .probe = px30_pmuclk_probe, 1884 }; 1885 1886 /** 1887 * soc_clk_dump() - Print clock frequencies 1888 * Returns zero on success 1889 * 1890 * Implementation for the clk dump command. 1891 */ 1892 int soc_clk_dump(void) 1893 { 1894 struct udevice *cru_dev, *pmucru_dev; 1895 struct px30_clk_priv *priv; 1896 const struct px30_clk_info *clk_dump; 1897 struct clk clk; 1898 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1899 unsigned long rate; 1900 int i, ret; 1901 1902 ret = uclass_get_device_by_driver(UCLASS_CLK, 1903 DM_GET_DRIVER(rockchip_px30_cru), 1904 &cru_dev); 1905 if (ret) { 1906 printf("%s failed to get cru device\n", __func__); 1907 return ret; 1908 } 1909 1910 ret = uclass_get_device_by_driver(UCLASS_CLK, 1911 DM_GET_DRIVER(rockchip_px30_pmucru), 1912 &pmucru_dev); 1913 if (ret) { 1914 printf("%s failed to get pmucru device\n", __func__); 1915 return ret; 1916 } 1917 1918 priv = dev_get_priv(cru_dev); 1919 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1920 priv->sync_kernel ? "sync kernel" : "uboot", 1921 priv->armclk_enter_hz / 1000, 1922 priv->armclk_init_hz / 1000, 1923 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 1924 priv->set_armclk_rate ? " KHz" : "N/A"); 1925 for (i = 0; i < clk_count; i++) { 1926 clk_dump = &clks_dump[i]; 1927 if (clk_dump->name) { 1928 clk.id = clk_dump->id; 1929 if (clk_dump->is_cru) 1930 ret = clk_request(cru_dev, &clk); 1931 else 1932 ret = clk_request(pmucru_dev, &clk); 1933 if (ret < 0) 1934 return ret; 1935 1936 rate = clk_get_rate(&clk); 1937 clk_free(&clk); 1938 if (i == 0) { 1939 if (rate < 0) 1940 printf(" %s %s\n", clk_dump->name, 1941 "unknown"); 1942 else 1943 printf(" %s %lu KHz\n", clk_dump->name, 1944 rate / 1000); 1945 } else { 1946 if (rate < 0) 1947 printf(" %s %s\n", clk_dump->name, 1948 "unknown"); 1949 else 1950 printf(" %s %lu KHz\n", clk_dump->name, 1951 rate / 1000); 1952 } 1953 } 1954 } 1955 1956 return 0; 1957 } 1958