1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 #include <linux/ioport.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define RK_PCIE_DBG 0 26 27 #define __pcie_dev_print_emit(fmt, ...) \ 28 ({ \ 29 printf(fmt, ##__VA_ARGS__); \ 30 }) 31 32 #ifdef dev_err 33 #undef dev_err 34 #define dev_err(dev, fmt, ...) \ 35 ({ \ 36 if (dev) \ 37 __pcie_dev_print_emit("%s: " fmt, dev->name, \ 38 ##__VA_ARGS__); \ 39 }) 40 #endif 41 42 #ifdef dev_info 43 #undef dev_info 44 #define dev_info dev_err 45 #endif 46 47 #ifdef DEBUG 48 #define dev_dbg dev_err 49 #else 50 #define dev_dbg(dev, fmt, ...) \ 51 ({ \ 52 if (0) \ 53 __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ 54 }) 55 #endif 56 57 struct rk_pcie { 58 struct udevice *dev; 59 struct udevice *vpcie3v3; 60 void *dbi_base; 61 void *apb_base; 62 void *cfg_base; 63 fdt_size_t cfg_size; 64 struct phy phy; 65 struct clk_bulk clks; 66 int first_busno; 67 struct reset_ctl_bulk rsts; 68 struct gpio_desc rst_gpio; 69 struct pci_region io; 70 struct pci_region mem; 71 struct pci_region mem64; 72 bool is_bifurcation; 73 u32 gen; 74 }; 75 76 enum { 77 PCIBIOS_SUCCESSFUL = 0x0000, 78 PCIBIOS_UNSUPPORTED = -ENODEV, 79 PCIBIOS_NODEV = -ENODEV, 80 }; 81 82 #define msleep(a) udelay((a) * 1000) 83 84 /* Parameters for the waiting for iATU enabled routine */ 85 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 86 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 87 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 88 #define PCIE_CLIENT_LTSSM_STATUS 0x300 89 #define SMLH_LINKUP BIT(16) 90 #define RDLH_LINKUP BIT(17) 91 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 92 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 93 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 94 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 95 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 96 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 97 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 98 #define PCIE_CLIENT_DBF_EN 0xffff0003 99 100 /* PCI DBICS registers */ 101 #define PCIE_LINK_STATUS_REG 0x80 102 #define PCIE_LINK_STATUS_SPEED_OFF 16 103 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 104 #define PCIE_LINK_STATUS_WIDTH_OFF 20 105 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 106 107 #define PCIE_LINK_CAPABILITY 0x7c 108 #define PCIE_LINK_CTL_2 0xa0 109 #define TARGET_LINK_SPEED_MASK 0xf 110 #define LINK_SPEED_GEN_1 0x1 111 #define LINK_SPEED_GEN_2 0x2 112 #define LINK_SPEED_GEN_3 0x3 113 114 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 115 #define PCIE_DBI_RO_WR_EN BIT(0) 116 117 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 118 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 119 120 /* 121 * iATU Unroll-specific register definitions 122 * From 4.80 core version the address translation will be made by unroll. 123 * The registers are offset from atu_base 124 */ 125 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 126 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 127 #define PCIE_ATU_UNR_LOWER_BASE 0x08 128 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 129 #define PCIE_ATU_UNR_LIMIT 0x10 130 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 131 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 132 133 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) 134 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 135 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 136 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 137 #define PCIE_ATU_TYPE_IO (0x2 << 0) 138 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 139 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 140 #define PCIE_ATU_ENABLE (0x1 << 31) 141 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 142 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 143 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 144 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 145 146 /* Register address builder */ 147 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 148 ((0x3 << 20) | ((region) << 9)) 149 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 150 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 151 152 /* Parameters for the waiting for iATU enabled routine */ 153 #define LINK_WAIT_MAX_IATU_RETRIES 5 154 #define LINK_WAIT_IATU 10000 155 156 #define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 157 158 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 159 { 160 if ((uintptr_t)addr & (size - 1)) { 161 *val = 0; 162 return PCIBIOS_UNSUPPORTED; 163 } 164 165 if (size == 4) { 166 *val = readl(addr); 167 } else if (size == 2) { 168 *val = readw(addr); 169 } else if (size == 1) { 170 *val = readb(addr); 171 } else { 172 *val = 0; 173 return PCIBIOS_NODEV; 174 } 175 176 return PCIBIOS_SUCCESSFUL; 177 } 178 179 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 180 { 181 if ((uintptr_t)addr & (size - 1)) 182 return PCIBIOS_UNSUPPORTED; 183 184 if (size == 4) 185 writel(val, addr); 186 else if (size == 2) 187 writew(val, addr); 188 else if (size == 1) 189 writeb(val, addr); 190 else 191 return PCIBIOS_NODEV; 192 193 return PCIBIOS_SUCCESSFUL; 194 } 195 196 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 197 u32 reg, size_t size) 198 { 199 int ret; 200 u32 val; 201 202 ret = rk_pcie_read(base + reg, size, &val); 203 if (ret) 204 dev_err(rk_pcie->dev, "Read APB address failed\n"); 205 206 return val; 207 } 208 209 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 210 u32 reg, size_t size, u32 val) 211 { 212 int ret; 213 214 ret = rk_pcie_write(base + reg, size, val); 215 if (ret) 216 dev_err(rk_pcie->dev, "Write APB address failed\n"); 217 } 218 219 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 220 { 221 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 222 } 223 224 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 225 u32 val) 226 { 227 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 228 } 229 230 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 231 { 232 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 233 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 234 } 235 236 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 237 { 238 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 239 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 240 } 241 242 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 243 u32 reg, u32 val) 244 { 245 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 246 void __iomem *base = rk_pcie->dbi_base; 247 248 writel(val, base + offset + reg); 249 } 250 251 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 252 { 253 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 254 void __iomem *base = rk_pcie->dbi_base; 255 256 return readl(base + offset + reg); 257 } 258 259 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 260 { 261 u32 val; 262 263 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 264 265 if (en) 266 val |= PCIE_DBI_RO_WR_EN; 267 else 268 val &= ~PCIE_DBI_RO_WR_EN; 269 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 270 } 271 272 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 273 { 274 u32 val; 275 276 rk_pcie_dbi_write_enable(rk_pcie, true); 277 278 /* setup RC BARs */ 279 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 280 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 281 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 282 283 /* setup interrupt pins */ 284 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 285 val &= 0xffff00ff; 286 val |= 0x00000100; 287 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 288 289 /* setup bus numbers */ 290 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 291 val &= 0xff000000; 292 val |= 0x00ff0100; 293 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 294 295 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 296 297 /* setup command register */ 298 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 299 val &= 0xffff0000; 300 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 301 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 302 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 303 304 /* program correct class for RC */ 305 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 306 /* Better disable write permission right after the update */ 307 308 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 309 val |= PORT_LOGIC_SPEED_CHANGE; 310 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 311 312 /* Disable BAR0 BAR1 */ 313 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4); 314 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4); 315 316 rk_pcie_dbi_write_enable(rk_pcie, false); 317 } 318 319 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) 320 { 321 u32 val; 322 323 rk_pcie_dbi_write_enable(pci, true); 324 325 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 326 val &= ~TARGET_LINK_SPEED_MASK; 327 val |= cap_speed; 328 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 329 330 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 331 val &= ~TARGET_LINK_SPEED_MASK; 332 val |= cap_speed; 333 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 334 335 rk_pcie_dbi_write_enable(pci, false); 336 } 337 338 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 339 int type, u64 cpu_addr, 340 u64 pci_addr, u32 size) 341 { 342 u32 retries, val; 343 344 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 345 index, type, cpu_addr, pci_addr, size); 346 347 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 348 lower_32_bits(cpu_addr)); 349 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 350 upper_32_bits(cpu_addr)); 351 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 352 lower_32_bits(cpu_addr + size - 1)); 353 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 354 lower_32_bits(pci_addr)); 355 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 356 upper_32_bits(pci_addr)); 357 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 358 type); 359 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 360 PCIE_ATU_ENABLE); 361 362 /* 363 * Make sure ATU enable takes effect before any subsequent config 364 * and I/O accesses. 365 */ 366 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 367 val = rk_pcie_readl_ob_unroll(pci, index, 368 PCIE_ATU_UNR_REGION_CTRL2); 369 if (val & PCIE_ATU_ENABLE) 370 return; 371 372 udelay(LINK_WAIT_IATU); 373 } 374 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 375 } 376 377 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 378 { 379 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 380 return 0; 381 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 382 return 0; 383 384 return 1; 385 } 386 387 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 388 pci_dev_t d, uint where) 389 { 390 int bus = PCI_BUS(d) - pcie->first_busno; 391 uintptr_t va_address; 392 u32 atu_type; 393 394 /* Use dbi_base for own configuration read and write */ 395 if (!bus) { 396 va_address = (uintptr_t)pcie->dbi_base; 397 goto out; 398 } 399 400 if (bus == 1) 401 /* 402 * For local bus whose primary bus number is root bridge, 403 * change TLP Type field to 4. 404 */ 405 atu_type = PCIE_ATU_TYPE_CFG0; 406 else 407 /* Otherwise, change TLP Type field to 5. */ 408 atu_type = PCIE_ATU_TYPE_CFG1; 409 410 /* 411 * Not accessing root port configuration space? 412 * Region #0 is used for Outbound CFG space access. 413 * Direction = Outbound 414 * Region Index = 0 415 */ 416 d = PCI_MASK_BUS(d); 417 d = PCI_ADD_BUS(bus, d); 418 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 419 atu_type, (u64)pcie->cfg_base, 420 d << 8, pcie->cfg_size); 421 422 va_address = (uintptr_t)pcie->cfg_base; 423 424 out: 425 va_address += where & ~0x3; 426 427 return va_address; 428 } 429 430 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 431 uint offset, ulong *valuep, 432 enum pci_size_t size) 433 { 434 struct rk_pcie *pcie = dev_get_priv(bus); 435 uintptr_t va_address; 436 ulong value; 437 438 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 439 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 440 441 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 442 debug("- out of range\n"); 443 *valuep = pci_get_ff(size); 444 return 0; 445 } 446 447 va_address = set_cfg_address(pcie, bdf, offset); 448 449 value = readl(va_address); 450 451 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 452 *valuep = pci_conv_32_to_size(value, offset, size); 453 454 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 455 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 456 pcie->io.bus_start, pcie->io.size); 457 458 return 0; 459 } 460 461 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 462 uint offset, ulong value, 463 enum pci_size_t size) 464 { 465 struct rk_pcie *pcie = dev_get_priv(bus); 466 uintptr_t va_address; 467 ulong old; 468 469 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 470 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 471 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 472 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 473 debug("- out of range\n"); 474 return 0; 475 } 476 477 va_address = set_cfg_address(pcie, bdf, offset); 478 479 old = readl(va_address); 480 value = pci_conv_size_to_32(old, value, offset, size); 481 writel(value, va_address); 482 483 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 484 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 485 pcie->io.bus_start, pcie->io.size); 486 487 return 0; 488 } 489 490 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 491 { 492 #if RK_PCIE_DBG 493 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 494 PCIE_CLIENT_DBG_TRANSITION_DATA); 495 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 496 PCIE_CLIENT_DBG_TRANSITION_DATA); 497 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 498 PCIE_CLIENT_DBG_TRANSITION_DATA); 499 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 500 PCIE_CLIENT_DBG_TRANSITION_DATA); 501 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 502 PCIE_CLIENT_DBF_EN); 503 #endif 504 } 505 506 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 507 { 508 #if RK_PCIE_DBG 509 u32 loop; 510 511 dev_err(rk_pcie->dev, "ltssm = 0x%x\n", 512 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 513 for (loop = 0; loop < 64; loop++) 514 dev_err(rk_pcie->dev, "fifo_status = 0x%x\n", 515 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 516 #endif 517 } 518 519 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 520 { 521 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 522 } 523 524 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 525 { 526 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 527 } 528 529 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 530 { 531 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 532 } 533 534 static int is_link_up(struct rk_pcie *priv) 535 { 536 u32 val; 537 538 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 539 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 540 (val & GENMASK(5, 0)) == 0x11) 541 return 1; 542 543 return 0; 544 } 545 546 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) 547 { 548 int retries; 549 550 if (is_link_up(priv)) { 551 printf("PCI Link already up before configuration!\n"); 552 return 1; 553 } 554 555 /* DW pre link configurations */ 556 rk_pcie_configure(priv, cap_speed); 557 558 /* Release the device */ 559 if (dm_gpio_is_valid(&priv->rst_gpio)) { 560 /* 561 * T_PVPERL (Power stable to PERST# inactive) should be a minimum of 100ms. 562 * We add a 200ms by default for sake of hoping everthings 563 * work fine. 564 */ 565 msleep(200); 566 dm_gpio_set_value(&priv->rst_gpio, 1); 567 /* 568 * Add this 20ms delay because we observe link is always up stably after it and 569 * could help us save 20ms for scanning devices. 570 */ 571 msleep(20); 572 } 573 574 rk_pcie_disable_ltssm(priv); 575 rk_pcie_link_status_clear(priv); 576 rk_pcie_enable_debug(priv); 577 578 /* Enable LTSSM */ 579 rk_pcie_enable_ltssm(priv); 580 581 for (retries = 0; retries < 50; retries++) { 582 if (is_link_up(priv)) { 583 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 584 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 585 rk_pcie_debug_dump(priv); 586 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 587 msleep(1000); 588 return 0; 589 } 590 591 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 592 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 593 rk_pcie_debug_dump(priv); 594 msleep(10); 595 } 596 597 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 598 rk_pcie_disable_ltssm(priv); 599 return -EINVAL; 600 } 601 602 static int rockchip_pcie_init_port(struct udevice *dev) 603 { 604 int ret; 605 u32 val; 606 struct rk_pcie *priv = dev_get_priv(dev); 607 union phy_configure_opts phy_cfg; 608 609 /* Rest the device */ 610 if (dm_gpio_is_valid(&priv->rst_gpio)) 611 dm_gpio_set_value(&priv->rst_gpio, 0); 612 613 /* Set power and maybe external ref clk input */ 614 if (priv->vpcie3v3) { 615 ret = regulator_set_enable(priv->vpcie3v3, true); 616 if (ret) { 617 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 618 ret); 619 return ret; 620 } 621 } 622 623 if (priv->is_bifurcation) { 624 phy_cfg.pcie.is_bifurcation = true; 625 ret = generic_phy_configure(&priv->phy, &phy_cfg); 626 if (ret) 627 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 628 } 629 630 ret = generic_phy_init(&priv->phy); 631 if (ret) { 632 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 633 goto err_disable_3v3; 634 } 635 636 ret = generic_phy_power_on(&priv->phy); 637 if (ret) { 638 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 639 goto err_exit_phy; 640 } 641 642 ret = reset_deassert_bulk(&priv->rsts); 643 if (ret) { 644 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 645 goto err_power_off_phy; 646 } 647 648 ret = clk_enable_bulk(&priv->clks); 649 if (ret) { 650 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 651 goto err_deassert_bulk; 652 } 653 654 /* LTSSM EN ctrl mode */ 655 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 656 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 657 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 658 659 /* Set RC mode */ 660 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 661 rk_pcie_setup_host(priv); 662 663 ret = rk_pcie_link_up(priv, priv->gen); 664 if (ret < 0) 665 goto err_link_up; 666 667 return 0; 668 err_link_up: 669 clk_disable_bulk(&priv->clks); 670 err_deassert_bulk: 671 reset_assert_bulk(&priv->rsts); 672 err_power_off_phy: 673 generic_phy_power_off(&priv->phy); 674 err_exit_phy: 675 generic_phy_exit(&priv->phy); 676 err_disable_3v3: 677 if(priv->vpcie3v3) 678 regulator_set_enable(priv->vpcie3v3, false); 679 return ret; 680 } 681 682 static int rockchip_pcie_parse_dt(struct udevice *dev) 683 { 684 struct rk_pcie *priv = dev_get_priv(dev); 685 u32 max_link_speed; 686 int ret; 687 struct resource res; 688 689 ret = dev_read_resource_byname(dev, "pcie-dbi", &res); 690 if (ret) 691 return -ENODEV; 692 priv->dbi_base = (void *)(res.start); 693 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 694 695 ret = dev_read_resource_byname(dev, "pcie-apb", &res); 696 if (ret) 697 return -ENODEV; 698 priv->apb_base = (void *)(res.start); 699 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 700 701 ret = gpio_request_by_name(dev, "reset-gpios", 0, 702 &priv->rst_gpio, GPIOD_IS_OUT); 703 if (ret) { 704 dev_err(dev, "failed to find reset-gpios property\n"); 705 return ret; 706 } 707 708 ret = reset_get_bulk(dev, &priv->rsts); 709 if (ret) { 710 dev_err(dev, "Can't get reset: %d\n", ret); 711 return ret; 712 } 713 714 ret = clk_get_bulk(dev, &priv->clks); 715 if (ret) { 716 dev_err(dev, "Can't get clock: %d\n", ret); 717 return ret; 718 } 719 720 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 721 &priv->vpcie3v3); 722 if (ret && ret != -ENOENT) { 723 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 724 return ret; 725 } 726 727 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 728 if (ret) { 729 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 730 return ret; 731 } 732 733 if (dev_read_bool(dev, "rockchip,bifurcation")) 734 priv->is_bifurcation = true; 735 736 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 737 if (ret < 0 || max_link_speed > 4) 738 priv->gen = 0; 739 else 740 priv->gen = max_link_speed; 741 742 return 0; 743 } 744 745 static int rockchip_pcie_probe(struct udevice *dev) 746 { 747 struct rk_pcie *priv = dev_get_priv(dev); 748 struct udevice *ctlr = pci_get_controller(dev); 749 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 750 int ret; 751 752 priv->first_busno = dev->seq; 753 priv->dev = dev; 754 755 ret = rockchip_pcie_parse_dt(dev); 756 if (ret) 757 return ret; 758 759 ret = rockchip_pcie_init_port(dev); 760 if (ret) 761 goto free_rst; 762 763 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 764 dev->seq, rk_pcie_get_link_speed(priv), 765 rk_pcie_get_link_width(priv), 766 hose->first_busno); 767 768 for (ret = 0; ret < hose->region_count; ret++) { 769 if (hose->regions[ret].flags == PCI_REGION_IO) { 770 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 771 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 772 priv->io.size = hose->regions[ret].size; /* IO size */ 773 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 774 if (upper_32_bits(hose->regions[ret].bus_start)) {/* MEM64 base */ 775 priv->mem64.phys_start = hose->regions[ret].phys_start; 776 priv->mem64.bus_start = hose->regions[ret].bus_start; 777 priv->mem64.size = hose->regions[ret].size; 778 } else { /* MEM32 base */ 779 priv->mem.phys_start = hose->regions[ret].phys_start; 780 priv->mem.bus_start = hose->regions[ret].bus_start; 781 priv->mem.size = hose->regions[ret].size; 782 } 783 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 784 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 785 priv->cfg_size = priv->io.size; 786 } else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) { 787 dev_err(dev, "don't support prefetchable memory, please fix your dtb.\n"); 788 } else { 789 dev_err(dev, "invalid flags type\n"); 790 } 791 } 792 793 #ifdef CONFIG_SYS_PCI_64BIT 794 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 795 priv->cfg_base, priv->cfg_base + priv->cfg_size, 796 priv->cfg_size); 797 798 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n", 799 priv->io.phys_start, priv->io.phys_start + priv->io.size, 800 priv->io.size); 801 802 dev_dbg(dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n", 803 priv->io.bus_start, priv->io.bus_start + priv->io.size, 804 priv->io.size); 805 806 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%llx]\n", 807 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 808 priv->mem.size); 809 810 dev_dbg(dev, "MEM32 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 811 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 812 priv->mem.size); 813 814 dev_dbg(dev, "MEM64 space: [0x%llx - 0x%llx, size 0x%llx]\n", 815 priv->mem64.phys_start, priv->mem64.phys_start + priv->mem64.size, 816 priv->mem64.size); 817 818 dev_dbg(dev, "MEM64 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 819 priv->mem64.bus_start, priv->mem64.bus_start + priv->mem64.size, 820 priv->mem64.size); 821 822 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX2, 823 PCIE_ATU_TYPE_MEM, 824 priv->mem64.phys_start, 825 priv->mem64.bus_start, priv->mem64.size); 826 #else 827 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 828 priv->cfg_base, priv->cfg_base + priv->cfg_size, 829 priv->cfg_size); 830 831 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 832 priv->io.phys_start, priv->io.phys_start + priv->io.size, 833 priv->io.size); 834 835 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 836 priv->io.bus_start, priv->io.bus_start + priv->io.size, 837 priv->io.size); 838 839 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%x]\n", 840 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 841 priv->mem.size); 842 843 dev_dbg(dev, "MEM32 bus: [0x%x - 0x%x, size 0x%x]\n", 844 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 845 priv->mem.size); 846 847 #endif 848 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 849 PCIE_ATU_TYPE_MEM, 850 priv->mem.phys_start, 851 priv->mem.bus_start, priv->mem.size); 852 853 return 0; 854 free_rst: 855 dm_gpio_free(dev, &priv->rst_gpio); 856 return ret; 857 } 858 859 static const struct dm_pci_ops rockchip_pcie_ops = { 860 .read_config = rockchip_pcie_rd_conf, 861 .write_config = rockchip_pcie_wr_conf, 862 }; 863 864 static const struct udevice_id rockchip_pcie_ids[] = { 865 { .compatible = "rockchip,rk3528-pcie" }, 866 { .compatible = "rockchip,rk3562-pcie" }, 867 { .compatible = "rockchip,rk3568-pcie" }, 868 { .compatible = "rockchip,rk3588-pcie" }, 869 { .compatible = "rockchip,rk3576-pcie" }, 870 { } 871 }; 872 873 U_BOOT_DRIVER(rockchip_pcie) = { 874 .name = "pcie_dw_rockchip", 875 .id = UCLASS_PCI, 876 .of_match = rockchip_pcie_ids, 877 .ops = &rockchip_pcie_ops, 878 .probe = rockchip_pcie_probe, 879 .priv_auto_alloc_size = sizeof(struct rk_pcie), 880 }; 881