1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .reg_done_frm = VOP_REG_VER(RK3288_SYS_CTRL1, 0x1, 24, 3, 7, -1), 92 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 93 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 94 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 95 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 96 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 97 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 98 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 100 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 101 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 102 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 103 104 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 105 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 106 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 107 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 108 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 109 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 110 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 111 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 112 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 113 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 114 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 115 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 116 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 117 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 118 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 119 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 120 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1), 121 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 122 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1), 123 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1), 124 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1), 125 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1), 126 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24), 127 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25), 128 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26), 129 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27), 130 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28), 131 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1), 132 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1), 133 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1), 134 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1), 135 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1), 136 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1), 137 138 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 139 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 140 141 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 142 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 143 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 144 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 145 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 146 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 147 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 148 149 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 150 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 151 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 152 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 153 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 154 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 155 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 156 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 157 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 158 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 159 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 160 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 161 162 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 163 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 164 165 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 166 167 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 168 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 169 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 170 }; 171 172 static const struct vop_line_flag rk3288_vop_line_flag = { 173 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 174 }; 175 176 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = { 177 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 13), 178 }; 179 180 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = { 181 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 15), 182 }; 183 184 const struct vop_data rk3288_vop_big = { 185 .version = VOP_VERSION(3, 1), 186 .max_output = {3840, 2160}, 187 .feature = VOP_FEATURE_OUTPUT_10BIT, 188 .ctrl = &rk3288_ctrl_data, 189 .grf_ctrl = &rk3288_vop_big_grf_ctrl, 190 .win = &rk3288_win01_data, 191 .line_flag = &rk3288_vop_line_flag, 192 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 193 }; 194 195 const struct vop_data rk3288_vop_lit = { 196 .version = VOP_VERSION(3, 1), 197 .max_output = {2560, 1600}, 198 .feature = VOP_FEATURE_OUTPUT_10BIT, 199 .ctrl = &rk3288_ctrl_data, 200 .grf_ctrl = &rk3288_vop_lit_grf_ctrl, 201 .win = &rk3288_win01_data, 202 .line_flag = &rk3288_vop_line_flag, 203 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 204 }; 205 206 static const struct vop_win rk3368_win23_data = { 207 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 208 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 209 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15), 210 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 211 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 212 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 213 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 214 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 215 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffff, 0), 216 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0), 217 }; 218 219 static const struct vop_line_flag rk3368_vop_line_flag = { 220 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 221 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 222 }; 223 224 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = { 225 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5), 226 }; 227 228 const struct vop_data rk3368_vop = { 229 .version = VOP_VERSION(3, 2), 230 .max_output = {4096, 2160}, 231 .ctrl = &rk3288_ctrl_data, 232 .grf_ctrl = &rk3368_vop_grf_ctrl, 233 .win = &rk3288_win01_data, 234 .line_flag = &rk3368_vop_line_flag, 235 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 236 }; 237 238 static const struct vop_line_flag rk3366_vop_line_flag = { 239 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 240 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 241 }; 242 243 const struct vop_data rk3366_vop = { 244 .version = VOP_VERSION(3, 4), 245 .max_output = {4096, 2160}, 246 .ctrl = &rk3288_ctrl_data, 247 .win = &rk3288_win01_data, 248 .line_flag = &rk3366_vop_line_flag, 249 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 250 }; 251 252 static const uint32_t vop_csc_r2y_bt601[] = { 253 0x02590132, 0xff530075, 0x0200fead, 0xfe530200, 254 0x0000ffad, 0x00000200, 0x00080200, 0x00080200, 255 }; 256 257 static const uint32_t vop_csc_r2y_bt601_12_235[] = { 258 0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87, 259 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200, 260 }; 261 262 static const uint32_t vop_csc_r2y_bt709[] = { 263 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2, 264 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200, 265 }; 266 267 static const uint32_t vop_csc_r2y_bt2020[] = { 268 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1, 269 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200, 270 }; 271 272 static const struct vop_csc_table rk3399_csc_table = { 273 .r2y_bt601 = vop_csc_r2y_bt601, 274 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235, 275 .r2y_bt709 = vop_csc_r2y_bt709, 276 .r2y_bt2020 = vop_csc_r2y_bt2020, 277 }; 278 279 static const struct vop_csc rk3399_win0_csc = { 280 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0), 281 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1), 282 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2), 283 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R, 284 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3, 285 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y, 286 }; 287 288 static const struct vop_csc rk3399_win2_csc = { 289 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16), 290 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 18), 291 .r2r_offset = RK3399_WIN2_YUV2YUV_3X3, 292 293 }; 294 295 const struct vop_data rk3399_vop_big = { 296 .version = VOP_VERSION(3, 5), 297 .max_output = {4096, 2160}, 298 .feature = VOP_FEATURE_OUTPUT_10BIT, 299 .ctrl = &rk3288_ctrl_data, 300 .win = &rk3288_win01_data, 301 .line_flag = &rk3366_vop_line_flag, 302 .csc_table = &rk3399_csc_table, 303 .win_csc = &rk3399_win0_csc, 304 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 305 }; 306 307 const struct vop_data rk3399_vop_lit = { 308 .version = VOP_VERSION(3, 6), 309 .max_output = {2560, 1600}, 310 .ctrl = &rk3288_ctrl_data, 311 .win = &rk3368_win23_data, 312 .line_flag = &rk3366_vop_line_flag, 313 .csc_table = &rk3399_csc_table, 314 .win_csc = &rk3399_win2_csc, 315 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 316 }; 317 318 const struct vop_data rk322x_vop = { 319 .version = VOP_VERSION(3, 7), 320 .max_output = {4096, 2160}, 321 .feature = VOP_FEATURE_OUTPUT_10BIT, 322 .ctrl = &rk3288_ctrl_data, 323 .win = &rk3288_win01_data, 324 .line_flag = &rk3366_vop_line_flag, 325 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 326 }; 327 328 static const struct vop_ctrl rk3328_ctrl_data = { 329 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 330 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 331 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 332 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 333 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 334 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 335 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 336 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 337 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 338 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 339 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 340 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 341 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 342 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 343 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 344 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 345 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 346 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 347 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 348 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 349 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 350 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 351 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 352 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 353 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 354 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 355 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 356 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 357 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 358 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 359 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 360 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 361 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 362 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 363 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 364 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 365 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 366 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 367 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 368 369 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 370 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 371 372 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 373 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 374 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 375 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 376 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 377 378 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 379 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 380 381 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 382 383 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 384 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 385 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 386 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 387 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 388 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 389 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 390 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 391 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 392 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 393 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 394 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 395 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 396 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 397 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 398 399 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 400 }; 401 402 403 static const struct vop_line_flag rk3328_vop_line_flag = { 404 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 405 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 406 }; 407 408 const struct vop_data rk3328_vop = { 409 .version = VOP_VERSION(3, 8), 410 .max_output = {4096, 2160}, 411 .feature = VOP_FEATURE_OUTPUT_10BIT, 412 .ctrl = &rk3328_ctrl_data, 413 .win = &rk3288_win01_data, 414 .win_offset = 0xd0, 415 .line_flag = &rk3328_vop_line_flag, 416 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 417 }; 418 419 static const struct vop_win rk3126_win1_data = { 420 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 421 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 422 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 423 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 424 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 425 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 426 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 427 }; 428 429 static const struct vop_ctrl rk3036_ctrl_data = { 430 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 431 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 432 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 433 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7), 434 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 435 .dither_down = VOP_REG(RK3036_DSP_CTRL0, 0x3, 10), 436 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 437 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 438 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 439 .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22), 440 .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23), 441 .hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4), 442 .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24), 443 .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25), 444 .lvds_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 26), 445 .lvds_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 27), 446 .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28), 447 .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29), 448 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 449 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 450 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 451 }; 452 453 static const struct vop_line_flag rk3036_vop_line_flag = { 454 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 455 }; 456 457 const struct vop_data rk3036_vop = { 458 .version = VOP_VERSION(2, 2), 459 .max_output = {1920, 1080}, 460 .ctrl = &rk3036_ctrl_data, 461 .win = &rk3126_win1_data, 462 .line_flag = &rk3036_vop_line_flag, 463 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 464 }; 465 466 static const struct vop_scl_regs rk3366_lit_win_scl = { 467 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 468 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 469 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 470 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 471 }; 472 473 static const struct vop_win rk3366_win0_data = { 474 .scl = &rk3366_lit_win_scl, 475 476 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 477 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 478 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 479 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 480 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 481 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 482 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 483 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 484 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 485 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 486 487 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 488 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 489 }; 490 491 static const struct vop_win rk3366_win1_data = { 492 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 493 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 494 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 495 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 496 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 497 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 498 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 499 500 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 501 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 502 }; 503 504 static const struct vop_ctrl px30_ctrl_data = { 505 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 506 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 507 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 508 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 509 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 510 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 511 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 512 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 513 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 514 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 515 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 516 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 517 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 518 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 519 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 520 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 521 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 522 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 523 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 524 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 525 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 526 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 527 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 528 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 529 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 530 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 531 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 532 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 533 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 534 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 535 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 536 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 537 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 538 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 539 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 540 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 541 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 542 543 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 544 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 545 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 546 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 547 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 548 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 549 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 550 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 551 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 552 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 553 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 554 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 555 556 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 557 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 558 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 559 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 560 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 561 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 562 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 563 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 564 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 565 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 566 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 567 568 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 569 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 570 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 571 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 572 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 573 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 574 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 575 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 576 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 577 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 578 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 579 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 580 0xffffffff, 0), 581 }; 582 583 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 584 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 585 }; 586 587 static const struct vop_grf_ctrl px30_grf_ctrl = { 588 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4), 589 }; 590 591 const struct vop_data px30_vop_lit = { 592 .version = VOP_VERSION(2, 5), 593 .max_output = {1920, 1080}, 594 .ctrl = &px30_ctrl_data, 595 .grf_ctrl = &px30_grf_ctrl, 596 .win = &rk3366_win1_data, 597 .line_flag = &rk3366_vop_lite_line_flag, 598 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 599 }; 600 601 const struct vop_data px30_vop_big = { 602 .version = VOP_VERSION(2, 6), 603 .max_output = {1920, 1080}, 604 .ctrl = &px30_ctrl_data, 605 .grf_ctrl = &px30_grf_ctrl, 606 .win = &rk3366_win1_data, 607 .line_flag = &rk3366_vop_lite_line_flag, 608 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 609 }; 610 611 static const struct vop_ctrl rk3308_ctrl_data = { 612 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 613 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 614 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 615 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 616 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 617 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 618 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 619 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 620 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 621 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 622 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 623 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3), 624 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 625 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 626 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 627 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 628 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 629 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 630 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 631 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 632 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 633 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 634 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 635 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 636 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 637 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 638 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 639 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 640 641 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 642 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 643 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 644 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 645 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 646 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 647 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 648 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 649 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 650 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 651 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 652 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 653 654 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 655 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 656 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 657 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 658 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 659 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 660 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 661 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 662 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 663 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 664 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 665 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 666 0xffffffff, 0), 667 }; 668 669 const struct vop_data rk3308_vop = { 670 .version = VOP_VERSION(2, 7), 671 .max_output = {1920, 1080}, 672 .ctrl = &rk3308_ctrl_data, 673 .win = &rk3366_win0_data, 674 .line_flag = &rk3366_vop_lite_line_flag, 675 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 676 }; 677 678 static const struct vop_grf_ctrl rk1808_grf_ctrl = { 679 .grf_dclk_inv = VOP_REG(RK1808_GRF_PD_VO_CON1, 0x1, 4), 680 }; 681 682 const struct vop_data rk1808_vop = { 683 .version = VOP_VERSION(2, 8), 684 .max_output = {1920, 1080}, 685 .ctrl = &px30_ctrl_data, 686 .grf_ctrl = &rk1808_grf_ctrl, 687 .win = &rk3366_win1_data, 688 .line_flag = &rk3366_vop_lite_line_flag, 689 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 690 }; 691 692 const struct vop_data rv1108_vop = { 693 .version = VOP_VERSION(2, 4), 694 .max_output = {1920, 1080}, 695 .ctrl = &rk3308_ctrl_data, 696 .win = &rk3366_win0_data, 697 .line_flag = &rk3366_vop_lite_line_flag, 698 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 699 }; 700 701 static const struct vop_win rv1126_win2_data = { 702 .gate = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 0), 703 .enable = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 4), 704 .format = VOP_REG(RV1126_WIN2_CTRL0, 0x3, 5), 705 .rb_swap = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 20), 706 .dsp_info = VOP_REG(RV1126_WIN2_DSP_INFO0, 0x0fff0fff, 0), 707 .dsp_st = VOP_REG(RV1126_WIN2_DSP_ST0, 0x1fff1fff, 0), 708 .yrgb_mst = VOP_REG(RV1126_WIN2_MST0, 0xffffffff, 0), 709 .yrgb_vir = VOP_REG(RV1126_WIN2_VIR0_1, 0x1fff, 0), 710 }; 711 712 static const struct vop_ctrl rv1126_ctrl_data = { 713 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 714 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 715 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 716 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 717 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 718 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 719 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 720 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 721 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 722 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 723 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 724 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 725 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22), 726 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 727 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 728 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 729 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 730 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 731 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 732 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 733 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 734 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 735 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 736 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 737 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 738 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 739 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 740 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 741 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), 742 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 743 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 744 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 745 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 746 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 747 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 748 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 749 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 750 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 751 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 752 753 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 754 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 755 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 756 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 757 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 758 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 759 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 760 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 761 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 762 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 763 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 764 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 765 766 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 767 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 768 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 769 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 770 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 771 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 772 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 773 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 774 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 775 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 776 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 777 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 778 0xffffffff, 0), 779 }; 780 781 const struct vop_data rv1126_vop = { 782 .version = VOP_VERSION(2, 7), 783 .max_output = {1920, 1080}, 784 .ctrl = &rv1126_ctrl_data, 785 .win = &rv1126_win2_data, 786 .line_flag = &rk3366_vop_lite_line_flag, 787 .reg_len = RK3366_LIT_FLAG_REG * 4, 788 }; 789