core: crypto: rename CFG_HWSUPP_PMULL to CFG_HWSUPP_PMULT_64

CFG_HWSUPP_PMULL is used to determine whether the CPU supports long
polynomial multiplies of 64-bit values, which means:
- for AArch64: P

core: crypto: rename CFG_HWSUPP_PMULL to CFG_HWSUPP_PMULT_64

CFG_HWSUPP_PMULL is used to determine whether the CPU supports long
polynomial multiplies of 64-bit values, which means:
- for AArch64: PMULL and PMULL2 with the 1Q arrangement specifier
- for AArch32: VMULL.P64
Otherwise, 8-bit polynomial multiplication is used instead.

Therefore, CFG_HWSUPP_PMULT_64 is a better name because it does not
seem to imply Aarch64 (no PMULL) and clearly states the 64-bit size.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto.h manages hash context memory

To ease integration with other crypto libraries change the hash context
interface in crypto.h to manage the memory used for the hash context.

Reviewed-by:

core: crypto.h manages hash context memory

To ease integration with other crypto libraries change the hash context
interface in crypto.h to manage the memory used for the hash context.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.p

Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.py --linaro-only --strip-license-text optee_os/

Link: [1] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Reformat copyright/license header in files with an SPDX ID

Some files were committed with an SPDX license identifier before the
rules were defined [1]. Reformat them accordingly.

[1] documentation/

Reformat copyright/license header in files with an SPDX ID

Some files were committed with an SPDX license identifier before the
rules were defined [1]. Reformat them accordingly.

[1] documentation/copyright_and_license_headers.rst

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: lpae: zero initialize all l1 tables

Fixes: 4cc2823eb25c ("core: user mode translation table")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.fo

core: lpae: zero initialize all l1 tables

Fixes: 4cc2823eb25c ("core: user mode translation table")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)

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core: rename mattr_uflags_to_str()

Renames mattr_uflags_to_str() to mattr_perm_to_str() and report all
permission bits using a 7 bytes long string instead.

This allows observing the permissions of

core: rename mattr_uflags_to_str()

Renames mattr_uflags_to_str() to mattr_perm_to_str() and report all
permission bits using a 7 bytes long string instead.

This allows observing the permissions of the minimal kernel mapping
added to the user space context.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make all mapping non-global

Makes all mapping non-global to avoid the otherwise required tlb
invalidation when switching to user mode.

This change makes the fix for CVE-2017-5754 complete.

R

core: make all mapping non-global

Makes all mapping non-global to avoid the otherwise required tlb
invalidation when switching to user mode.

This change makes the fix for CVE-2017-5754 complete.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use minimal kernel map in user space

Adds a trampoline in the exception vector to switch to a minimal kernel
map when in user mode. When returning to kernel mode the full kernel
mode map is re

core: use minimal kernel map in user space

Adds a trampoline in the exception vector to switch to a minimal kernel
map when in user mode. When returning to kernel mode the full kernel
mode map is restored.

Arm32 tries to mimic the arm64 exception model somewhat by letting each
exception handler run with disabled asynchronous aborts, irq and fiq.

Form arm32 accesses to the cpus thread_core_local is only done via the
stack pointer in abort mode. Entry of user mode is only done via abort
mode, that means that the abort mode spsr register carries the new cpsr.
Care is taken to have all exceptions disabled while using abort mode.

ASIDs are paired with a user mode ASID with lowest bit sset and a
kernel mode ASID with the lowest bit cleared.

ASID 0 is reserved for kernel mode use when there's no user mode mapping
active.

With this change an active used mode mapping while in kernel mode uses
(asid | 0), and while in user mode (asid | 1). The switch is done via
the trampoline in the vector.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread_a32.S: move intr handler macros

Moves the interrupt handler macros closer to the vector.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jero

core: thread_a32.S: move intr handler macros

Moves the interrupt handler macros closer to the vector.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: exception handlers in one section

Moves all exception handlers into the section of the vector,
.text.thread_vect_table. This makes it possible to later map just the
exception vector and

core: arm32: exception handlers in one section

Moves all exception handlers into the section of the vector,
.text.thread_vect_table. This makes it possible to later map just the
exception vector and the closest associated code while in user mode.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: user mode translation table

Adds a second translation table to be used while in user mode containing
user mode mapping and a minimal kernel mapping.

Reviewed-by: Etienne Carriere <etienne.car

core: user mode translation table

Adds a second translation table to be used while in user mode containing
user mode mapping and a minimal kernel mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: add kernel mapping to user map

Adds a minimal kernel mapping needed when user mapping is active.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew

core: mm: add kernel mapping to user map

Adds a minimal kernel mapping needed when user mapping is active.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread: add thread_get_user_kcode()

Adds thread_get_user_kcode() to report required kernel mapping
(exception vector and some associated code in the same section as the
vector) inside a user m

core: thread: add thread_get_user_kcode()

Adds thread_get_user_kcode() to report required kernel mapping
(exception vector and some associated code in the same section as the
vector) inside a user mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add mobj_tee_ram

Adds mobj_tee_ram to describe TEE RAM mapping inside a user mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissi

core: add mobj_tee_ram

Adds mobj_tee_ram to describe TEE RAM mapping inside a user mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tlbi_asid() handle kernel mode ASID too

When invalidating an ASID (lowest bit 0), clear the paired ASID (lowest
bit 1)too.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed

core: tlbi_asid() handle kernel mode ASID too

When invalidating an ASID (lowest bit 0), clear the paired ASID (lowest
bit 1)too.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: refactor ASID management

Refactors Address Space Identifier management. The field in struct
user_ta_ctx is moved into struct tee_mmu_info and renamed to asid.

Allocation refactored internally

core: refactor ASID management

Refactors Address Space Identifier management. The field in struct
user_ta_ctx is moved into struct tee_mmu_info and renamed to asid.

Allocation refactored internally with asid_alloc() and asid_free()
functions, based on bitstring.h macros.

ASIDs starts at 2, and is always an even number.

ASIDs with the lowest bit set is reserved for as the second ASID when
using ASIDs in pairs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make core_mmu.h asm friendly

Makes core_mmu.h assembly friendly by excluding C code with #ifndef ASM

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier

core: make core_mmu.h asm friendly

Makes core_mmu.h assembly friendly by excluding C code with #ifndef ASM

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32_macros.S: add {read,write}_ttbr0_64bit

Adds the macros read_ttbr0_64bit and write_ttbr0_64bit

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <

core: arm32_macros.S: add {read,write}_ttbr0_64bit

Adds the macros read_ttbr0_64bit and write_ttbr0_64bit

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32_macros.S: add {read,write}_tpidrprw

Adds the assembly macros write_tpidrprw and read_tpidrprw to access the
TPIDRPRW register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org

core: arm32_macros.S: add {read,write}_tpidrprw

Adds the assembly macros write_tpidrprw and read_tpidrprw to access the
TPIDRPRW register.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: sm: invalidate branch predictor

If build with secure monitor and CFG_CORE_WORKAROUND_SPECTRE_BP=y
invalidate branch predictor on non-secure entry.

Fixes CVE-2017-5715

Reviewed-by: Jer

core: arm32: sm: invalidate branch predictor

If build with secure monitor and CFG_CORE_WORKAROUND_SPECTRE_BP=y
invalidate branch predictor on non-secure entry.

Fixes CVE-2017-5715

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread.h: reorder struct thread_core_local

Reorders elements in struct thread_core_local to make sure that:
uint32_t r[2];
is double word (8) aligned for ARM32 since the strd instruction
somet

core: thread.h: reorder struct thread_core_local

Reorders elements in struct thread_core_local to make sure that:
uint32_t r[2];
is double word (8) aligned for ARM32 since the strd instruction
sometimes is used to write to that element.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread_a32.S: remove useless .section

Removes the useless .section .text.thread_asm

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@l

core: thread_a32.S: remove useless .section

Removes the useless .section .text.thread_asm

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: treat size fault as translation fault

AArch64 is very specific regarding different data/prefetch exceptions.
With this patch recognize Address Size faults and treat them as
translation

core: arm64: treat size fault as translation fault

AArch64 is very specific regarding different data/prefetch exceptions.
With this patch recognize Address Size faults and treat them as
translation faults.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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