1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <arm32.h> 30#include <arm32_macros.S> 31#include <arm32_macros_cortex_a9.S> 32#include <asm.S> 33#include <kernel/tz_ssvce_def.h> 34#include <kernel/unwind.h> 35#include <platform_config.h> 36 37.section .text 38.balign 4 39.code 32 40 41/* 42 * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function 43 * 44 * If PL310 supports FZLW, enable also FZL in A9 core 45 * 46 * Use scratables registers R0-R3. 47 * No stack usage. 48 * LR store return address. 49 * Trap CPU in case of error. 50 * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) 51 */ 52FUNC arm_cl2_enable , : 53UNWIND( .fnstart) 54 55 /* Enable PL310 ctrl -> only set lsb bit */ 56 mov r1, #0x1 57 str r1, [r0, #PL310_CTRL] 58 59 /* if L2 FLZW enable, enable in L1 */ 60 ldr r1, [r0, #PL310_AUX_CTRL] 61 tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ 62 read_actlr r0 63 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ 64 write_actlr r0 65 66 mov pc, lr 67 68UNWIND( .fnend) 69END_FUNC arm_cl2_enable 70 71/* 72 * Cortex A9 configuration early configuration 73 * 74 * Use scratables registers R0-R3. 75 * No stack usage. 76 * LR store return address. 77 * Trap CPU in case of error. 78 */ 79FUNC plat_cpu_reset_early , : 80UNWIND( .fnstart) 81 82 mov_imm r0, CPU_SCTLR_INIT 83 write_sctlr r0 84 85 mov_imm r0, CPU_ACTLR_INIT 86 write_actlr r0 87 88 mov_imm r0, CPU_NSACR_INIT 89 write_nsacr r0 90 91 mov_imm r0, CPU_PCR_INIT 92 write_pcr r0 93 94 mov pc, lr 95 96UNWIND( .fnend) 97END_FUNC plat_cpu_reset_early 98 99