1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 31 #include <arm.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/ns16550.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <kernel/thread.h> 41 #include <kernel/tz_ssvce_def.h> 42 #include <mm/core_memprot.h> 43 #include <sm/optee_smc.h> 44 #include <tee/entry_fast.h> 45 #include <tee/entry_std.h> 46 47 static void main_fiq(void); 48 49 static const struct thread_handlers handlers = { 50 .std_smc = tee_entry_std, 51 .fast_smc = tee_entry_fast, 52 .nintr = main_fiq, 53 #if defined(CFG_WITH_ARM_TRUSTED_FW) 54 .cpu_on = cpu_on_handler, 55 .cpu_off = pm_do_nothing, 56 .cpu_suspend = pm_do_nothing, 57 .cpu_resume = pm_do_nothing, 58 .system_off = pm_do_nothing, 59 .system_reset = pm_do_nothing, 60 #else 61 .cpu_on = pm_panic, 62 .cpu_off = pm_panic, 63 .cpu_suspend = pm_panic, 64 .cpu_resume = pm_panic, 65 .system_off = pm_panic, 66 .system_reset = pm_panic, 67 #endif 68 }; 69 70 static struct gic_data gic_data; 71 static struct ns16550_data console_data; 72 73 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 74 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 75 76 const struct thread_handlers *generic_boot_get_handlers(void) 77 { 78 return &handlers; 79 } 80 81 static void main_fiq(void) 82 { 83 panic(); 84 } 85 86 #ifdef CFG_ARM32_core 87 void plat_cpu_reset_late(void) 88 { 89 static uint32_t cntfrq; 90 vaddr_t addr; 91 92 if (!get_core_pos()) { 93 /* read cnt freq */ 94 cntfrq = read_cntfrq(); 95 96 #if defined(CFG_BOOT_SECONDARY_REQUEST) 97 /* set secondary entry address */ 98 write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR), 99 DCFG_BASE + DCFG_SCRATCHRW1); 100 101 /* release secondary cores */ 102 write32(__compiler_bswap32(0x1 << 1), /* cpu1 */ 103 DCFG_BASE + DCFG_CCSR_BRR); 104 dsb(); 105 sev(); 106 #endif 107 108 /* configure CSU */ 109 110 /* first grant all peripherals */ 111 for (addr = CSU_BASE + CSU_CSL_START; 112 addr != CSU_BASE + CSU_CSL_END; 113 addr += 4) 114 write32(__compiler_bswap32(CSU_ACCESS_ALL), addr); 115 116 /* restrict key preipherals from NS */ 117 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 118 CSU_BASE + CSU_CSL30); 119 write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY), 120 CSU_BASE + CSU_CSL37); 121 122 /* lock the settings */ 123 for (addr = CSU_BASE + CSU_CSL_START; 124 addr != CSU_BASE + CSU_CSL_END; 125 addr += 4) 126 write32(read32(addr) | 127 __compiler_bswap32(CSU_SETTING_LOCK), 128 addr); 129 } else { 130 /* program the cntfrq, the cntfrq is banked for each core */ 131 write_cntfrq(cntfrq); 132 } 133 } 134 #endif 135 136 void console_init(void) 137 { 138 ns16550_init(&console_data, CONSOLE_UART_BASE); 139 register_serial_console(&console_data.chip); 140 } 141 142 void main_init_gic(void) 143 { 144 vaddr_t gicc_base; 145 vaddr_t gicd_base; 146 147 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 148 MEM_AREA_IO_SEC); 149 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 150 MEM_AREA_IO_SEC); 151 152 if (!gicc_base || !gicd_base) 153 panic(); 154 155 /* Initialize GIC */ 156 gic_init(&gic_data, gicc_base, gicd_base); 157 itr_init(&gic_data.chip); 158 } 159 160 void main_secondary_init_gic(void) 161 { 162 gic_cpu_init(&gic_data); 163 } 164