1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 * All rights reserved. 6 * 7 * Peng Fan <peng.fan@nxp.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <console.h> 33 #include <io.h> 34 #include <imx.h> 35 #include <mm/core_mmu.h> 36 #include <mm/core_memprot.h> 37 #include <platform_config.h> 38 39 static uint32_t imx_digproc(void) 40 { 41 static uint32_t reg; 42 vaddr_t anatop_addr; 43 44 if (!reg) { 45 anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC); 46 47 /* TODO: Handle SL here */ 48 #ifdef CFG_MX7 49 reg = read32(anatop_addr + OFFSET_DIGPROG_IMX7D); 50 #else 51 reg = read32(anatop_addr + OFFSET_DIGPROG); 52 #endif 53 } 54 55 return reg; 56 } 57 58 static uint32_t imx_soc_rev_major(void) 59 { 60 return ((imx_digproc() & 0xff00) >> 8) + 1; 61 } 62 63 uint32_t imx_soc_type(void) 64 { 65 return (imx_digproc() >> 16) & 0xff; 66 } 67 68 bool soc_is_imx6ul(void) 69 { 70 return imx_soc_type() == SOC_MX6UL; 71 } 72 73 bool soc_is_imx6ull(void) 74 { 75 return imx_soc_type() == SOC_MX6ULL; 76 } 77 78 bool soc_is_imx6sdl(void) 79 { 80 return imx_soc_type() == SOC_MX6DL; 81 } 82 83 bool soc_is_imx6dq(void) 84 { 85 return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 1); 86 } 87 88 bool soc_is_imx6dqp(void) 89 { 90 return (imx_soc_type() == SOC_MX6Q) && (imx_soc_rev_major() == 2); 91 } 92 93 bool soc_is_imx7ds(void) 94 { 95 return imx_soc_type() == SOC_MX7D; 96 } 97 98 uint32_t imx_get_src_gpr(int cpu) 99 { 100 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); 101 102 if (soc_is_imx7ds()) 103 return read32(va + SRC_GPR1_MX7 + cpu * 8 + 4); 104 else 105 return read32(va + SRC_GPR1 + cpu * 8 + 4); 106 } 107 108 void imx_set_src_gpr(int cpu, uint32_t val) 109 { 110 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC); 111 112 if (soc_is_imx7ds()) 113 write32(val, va + SRC_GPR1_MX7 + cpu * 8 + 4); 114 else 115 write32(val, va + SRC_GPR1 + cpu * 8 + 4); 116 } 117