1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <platform_config.h> 30 #include <console.h> 31 #include <stdint.h> 32 #include <string.h> 33 #include <assert.h> 34 #include <drivers/gic.h> 35 #include <drivers/serial8250_uart.h> 36 #include <arm.h> 37 #include <kernel/generic_boot.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <trace.h> 41 #include <kernel/misc.h> 42 #include <kernel/mutex.h> 43 #include <kernel/tee_time.h> 44 #include <kernel/tee_common_otp.h> 45 #include <mm/core_mmu.h> 46 #include <mm/core_memprot.h> 47 #include <tee/entry_std.h> 48 #include <tee/entry_fast.h> 49 #include <console.h> 50 #include <sm/sm.h> 51 52 #define PLAT_HW_UNIQUE_KEY_LENGTH 32 53 54 static struct gic_data gic_data; 55 static struct serial8250_uart_data console_data; 56 static uint8_t plat_huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 57 58 register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, CFG_TEE_RAM_VA_SIZE); 59 register_phys_mem(MEM_AREA_IO_SEC, SECRAM_BASE, SECRAM_SIZE); 60 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GICC_SIZE); 61 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GICD_SIZE); 62 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 63 SERIAL8250_UART_REG_SIZE); 64 65 void main_init_gic(void) 66 { 67 vaddr_t gicc_base; 68 vaddr_t gicd_base; 69 70 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC); 71 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC); 72 73 if (!gicc_base || !gicd_base) 74 panic(); 75 76 gic_init(&gic_data, gicc_base, gicd_base); 77 itr_init(&gic_data.chip); 78 } 79 80 void main_secondary_init_gic(void) 81 { 82 gic_cpu_init(&gic_data); 83 } 84 85 static void main_fiq(void) 86 { 87 gic_it_handle(&gic_data); 88 } 89 90 static const struct thread_handlers handlers = { 91 .std_smc = tee_entry_std, 92 .fast_smc = tee_entry_fast, 93 .nintr = main_fiq, 94 .cpu_on = pm_panic, 95 .cpu_off = pm_panic, 96 .cpu_suspend = pm_panic, 97 .cpu_resume = pm_panic, 98 .system_off = pm_panic, 99 .system_reset = pm_panic, 100 }; 101 102 const struct thread_handlers *generic_boot_get_handlers(void) 103 { 104 return &handlers; 105 } 106 107 struct plat_nsec_ctx { 108 uint32_t usr_sp; 109 uint32_t usr_lr; 110 uint32_t svc_sp; 111 uint32_t svc_lr; 112 uint32_t svc_spsr; 113 uint32_t abt_sp; 114 uint32_t abt_lr; 115 uint32_t abt_spsr; 116 uint32_t und_sp; 117 uint32_t und_lr; 118 uint32_t und_spsr; 119 uint32_t irq_sp; 120 uint32_t irq_lr; 121 uint32_t irq_spsr; 122 uint32_t fiq_sp; 123 uint32_t fiq_lr; 124 uint32_t fiq_spsr; 125 uint32_t fiq_rx[5]; 126 uint32_t mon_lr; 127 uint32_t mon_spsr; 128 }; 129 130 struct plat_boot_args { 131 struct plat_nsec_ctx nsec_ctx; 132 uint8_t huk[PLAT_HW_UNIQUE_KEY_LENGTH]; 133 }; 134 135 void init_sec_mon(unsigned long nsec_entry) 136 { 137 struct plat_boot_args *plat_boot_args; 138 struct sm_nsec_ctx *nsec_ctx; 139 140 plat_boot_args = phys_to_virt(nsec_entry, MEM_AREA_IO_SEC); 141 if (!plat_boot_args) 142 panic(); 143 144 /* Invalidate cache to fetch data from external memory */ 145 cache_op_inner(DCACHE_AREA_INVALIDATE, 146 plat_boot_args, sizeof(*plat_boot_args)); 147 148 /* Initialize secure monitor */ 149 nsec_ctx = sm_get_nsec_ctx(); 150 151 nsec_ctx->mode_regs.usr_sp = plat_boot_args->nsec_ctx.usr_sp; 152 nsec_ctx->mode_regs.usr_lr = plat_boot_args->nsec_ctx.usr_lr; 153 nsec_ctx->mode_regs.irq_spsr = plat_boot_args->nsec_ctx.irq_spsr; 154 nsec_ctx->mode_regs.irq_sp = plat_boot_args->nsec_ctx.irq_sp; 155 nsec_ctx->mode_regs.irq_lr = plat_boot_args->nsec_ctx.irq_lr; 156 nsec_ctx->mode_regs.svc_spsr = plat_boot_args->nsec_ctx.svc_spsr; 157 nsec_ctx->mode_regs.svc_sp = plat_boot_args->nsec_ctx.svc_sp; 158 nsec_ctx->mode_regs.svc_lr = plat_boot_args->nsec_ctx.svc_lr; 159 nsec_ctx->mode_regs.abt_spsr = plat_boot_args->nsec_ctx.abt_spsr; 160 nsec_ctx->mode_regs.abt_sp = plat_boot_args->nsec_ctx.abt_sp; 161 nsec_ctx->mode_regs.abt_lr = plat_boot_args->nsec_ctx.abt_lr; 162 nsec_ctx->mode_regs.und_spsr = plat_boot_args->nsec_ctx.und_spsr; 163 nsec_ctx->mode_regs.und_sp = plat_boot_args->nsec_ctx.und_sp; 164 nsec_ctx->mode_regs.und_lr = plat_boot_args->nsec_ctx.und_lr; 165 nsec_ctx->mon_lr = plat_boot_args->nsec_ctx.mon_lr; 166 nsec_ctx->mon_spsr = plat_boot_args->nsec_ctx.mon_spsr; 167 168 memcpy(plat_huk, plat_boot_args->huk, sizeof(plat_boot_args->huk)); 169 } 170 171 void console_init(void) 172 { 173 serial8250_uart_init(&console_data, CONSOLE_UART_BASE, 174 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 175 register_serial_console(&console_data.chip); 176 } 177 178 #if defined(CFG_OTP_SUPPORT) 179 180 void tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 181 { 182 memcpy(&hwkey->data[0], &plat_huk[0], sizeof(hwkey->data)); 183 } 184 185 #endif 186