1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * All rights reserved. 5 */ 6 #include <assert.h> 7 #include <drivers/hi16xx_uart.h> 8 #include <io.h> 9 #include <keep.h> 10 #include <mm/core_mmu.h> 11 #include <util.h> 12 13 /* Register offsets */ 14 15 #define UART_RBR 0x00 /* RX data buffer register */ 16 #define UART_THR 0x00 /* TX data buffer register */ 17 #define UART_DLL 0x00 /* Lower-bit frequency divider register */ 18 19 #define UART_IEL 0x04 /* Interrupt enable register */ 20 #define UART_DLH 0x04 /* Upper-bit frequency divider register */ 21 22 #define UART_FCR 0x08 /* FIFO control register */ 23 24 #define UART_LCR 0x0C /* Line control register */ 25 26 #define UART_LSR 0x14 /* Line status register */ 27 28 #define UART_USR 0x7C /* Status register */ 29 30 /* 31 * Line control register 32 */ 33 34 /* Data length selection */ 35 #define UART_LCR_DLS5 0x0 /* 5 bits */ 36 #define UART_LCR_DLS6 0x1 /* 6 bits */ 37 #define UART_LCR_DLS7 0x2 /* 7 bits */ 38 #define UART_LCR_DLS8 0x3 /* 8 bits */ 39 40 /* Enable access to UART_DLL and UART_DLH */ 41 #define UART_LCR_DLAB 0x80 42 43 /* 44 * FIFO control register 45 */ 46 47 #define UART_FCR_FIFO_EN 0x1 /* Enable FIFO (depth: 32 bytes) */ 48 #define UART_FCR_RX_FIFO_RST 0x2 /* Clear receive FIFO (auto reset) */ 49 #define UART_FCR_TX_FIFO_RST 0x4 /* Clear send FIFO (auto reset) */ 50 51 52 /* 53 * Status register 54 */ 55 56 #define UART_USR_BUSY_BIT 0 /* 0: idle/non-activated, 1: busy */ 57 #define UART_USR_TFNF_BIT 1 /* Transmit FIFO not full bit */ 58 #define UART_USR_TFE_BIT 2 /* Transmit FIFO empty bit */ 59 #define UART_USR_RFNE_BIT 3 /* Receive FIFO not empty bit */ 60 #define UART_USR_RFF_BIT 4 /* Receive FIFO full bit */ 61 62 static vaddr_t chip_to_base(struct serial_chip *chip) 63 { 64 struct hi16xx_uart_data *pd = 65 container_of(chip, struct hi16xx_uart_data, chip); 66 67 return io_pa_or_va(&pd->base); 68 } 69 70 static void hi16xx_uart_flush(struct serial_chip *chip) 71 { 72 vaddr_t base = chip_to_base(chip); 73 74 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 75 ; 76 } 77 78 static void hi16xx_uart_putc(struct serial_chip *chip, int ch) 79 { 80 vaddr_t base = chip_to_base(chip); 81 82 /* Wait until TX FIFO is empty */ 83 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 84 ; 85 86 /* Put character into TX FIFO */ 87 write32(ch & 0xFF, base + UART_THR); 88 } 89 90 static bool hi16xx_uart_have_rx_data(struct serial_chip *chip) 91 { 92 vaddr_t base = chip_to_base(chip); 93 94 return (read32(base + UART_USR) & UART_USR_RFNE_BIT); 95 } 96 97 static int hi16xx_uart_getchar(struct serial_chip *chip) 98 { 99 vaddr_t base = chip_to_base(chip); 100 101 while (!hi16xx_uart_have_rx_data(chip)) 102 ; 103 return read32(base + UART_RBR) & 0xFF; 104 } 105 106 static const struct serial_ops hi16xx_uart_ops = { 107 .flush = hi16xx_uart_flush, 108 .getchar = hi16xx_uart_getchar, 109 .have_rx_data = hi16xx_uart_have_rx_data, 110 .putc = hi16xx_uart_putc, 111 }; 112 KEEP_PAGER(hi16xx_uart_ops); 113 114 void hi16xx_uart_init(struct hi16xx_uart_data *pd, paddr_t base, 115 uint32_t uart_clk, uint32_t baud_rate) 116 { 117 uint16_t freq_div = uart_clk / (16 * baud_rate); 118 119 pd->base.pa = base; 120 pd->chip.ops = &hi16xx_uart_ops; 121 122 /* Enable (and clear) FIFOs */ 123 write32(UART_FCR_FIFO_EN, base + UART_FCR); 124 125 /* Enable access to _DLL and _DLH */ 126 write32(UART_LCR_DLAB, base + UART_LCR); 127 128 /* Calculate and set UART_DLL */ 129 write32(freq_div & 0xFF, base + UART_DLL); 130 131 /* Calculate and set UART_DLH */ 132 write32((freq_div >> 8) & 0xFF, base + UART_DLH); 133 134 /* Clear _DLL/_DLH access bit, set data size (8 bits), parity etc. */ 135 write32(UART_LCR_DLS8, base + UART_LCR); 136 137 /* Disable interrupt mode */ 138 write32(0, base + UART_IEL); 139 140 hi16xx_uart_flush(&pd->chip); 141 } 142 143