1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* Please keep them sorted based on the CRn register */ 30 31 .macro read_midr reg 32 mrc p15, 0, \reg, c0, c0, 0 33 .endm 34 35 .macro read_ctr reg 36 mrc p15, 0, \reg, c0, c0, 1 37 .endm 38 39 .macro read_mpidr reg 40 mrc p15, 0, \reg, c0, c0, 5 41 .endm 42 43 .macro read_sctlr reg 44 mrc p15, 0, \reg, c1, c0, 0 45 .endm 46 47 .macro write_sctlr reg 48 mcr p15, 0, \reg, c1, c0, 0 49 .endm 50 51 .macro write_actlr reg 52 mcr p15, 0, \reg, c1, c0, 1 53 .endm 54 55 .macro read_actlr reg 56 mrc p15, 0, \reg, c1, c0, 1 57 .endm 58 59 .macro write_cpacr reg 60 mcr p15, 0, \reg, c1, c0, 2 61 .endm 62 63 .macro read_cpacr reg 64 mrc p15, 0, \reg, c1, c0, 2 65 .endm 66 67 .macro read_scr reg 68 mrc p15, 0, \reg, c1, c1, 0 69 .endm 70 71 .macro write_scr reg 72 mcr p15, 0, \reg, c1, c1, 0 73 .endm 74 75 .macro write_nsacr reg 76 mcr p15, 0, \reg, c1, c1, 2 77 .endm 78 79 .macro read_nsacr reg 80 mrc p15, 0, \reg, c1, c1, 2 81 .endm 82 83 .macro write_ttbr0 reg 84 mcr p15, 0, \reg, c2, c0, 0 85 .endm 86 87 .macro write_ttbr0_64bit reg0, reg1 88 mcrr p15, 0, \reg0, \reg1, cr2 89 .endm 90 91 .macro read_ttbr0 reg 92 mrc p15, 0, \reg, c2, c0, 0 93 .endm 94 95 .macro read_ttbr0_64bit reg0, reg1 96 mrrc p15, 0, \reg0, \reg1, cr2 97 .endm 98 99 .macro write_ttbr1 reg 100 mcr p15, 0, \reg, c2, c0, 1 101 .endm 102 103 .macro read_ttbr1 reg 104 mrc p15, 0, \reg, c2, c0, 1 105 .endm 106 107 .macro write_ttbcr reg 108 mcr p15, 0, \reg, c2, c0, 2 109 .endm 110 111 .macro read_ttbcr reg 112 mrc p15, 0, \reg, c2, c0, 2 113 .endm 114 115 116 .macro write_dacr reg 117 mcr p15, 0, \reg, c3, c0, 0 118 .endm 119 120 .macro read_dacr reg 121 mrc p15, 0, \reg, c3, c0, 0 122 .endm 123 124 .macro read_dfsr reg 125 mrc p15, 0, \reg, c5, c0, 0 126 .endm 127 128 .macro write_icialluis 129 /* 130 * Invalidate all instruction caches to PoU, Inner Shareable 131 * (register ignored) 132 */ 133 mcr p15, 0, r0, c7, c1, 0 134 .endm 135 136 .macro write_bpiallis 137 /* 138 * Invalidate entire branch predictor array, Inner Shareable 139 * (register ignored) 140 */ 141 mcr p15, 0, r0, c7, c1, 6 142 .endm 143 144 .macro write_iciallu 145 /* Invalidate all instruction caches to PoU (register ignored) */ 146 mcr p15, 0, r0, c7, c5, 0 147 .endm 148 149 .macro write_icimvau reg 150 /* Instruction cache invalidate by MVA */ 151 mcr p15, 0, \reg, c7, c5, 1 152 .endm 153 154 .macro write_bpiall 155 /* Invalidate entire branch predictor array (register ignored) */ 156 mcr p15, 0, r0, c7, c5, 6 157 .endm 158 159 .macro write_dcimvac reg 160 /* Data cache invalidate by MVA */ 161 mcr p15, 0, \reg, c7, c6, 1 162 .endm 163 164 .macro write_dcisw reg 165 /* Data cache invalidate by set/way */ 166 mcr p15, 0, \reg, c7, c6, 2 167 .endm 168 169 .macro write_dccmvac reg 170 /* Data cache clean by MVA */ 171 mcr p15, 0, \reg, c7, c10, 1 172 .endm 173 174 .macro write_dccsw reg 175 /* Data cache clean by set/way */ 176 mcr p15, 0, \reg, c7, c10, 2 177 .endm 178 179 .macro write_dccimvac reg 180 /* Data cache invalidate by MVA */ 181 mcr p15, 0, \reg, c7, c14, 1 182 .endm 183 184 .macro write_dccisw reg 185 /* Data cache clean and invalidate by set/way */ 186 mcr p15, 0, \reg, c7, c14, 2 187 .endm 188 189 .macro write_tlbiall 190 /* Invalidate entire unified TLB (register ignored) */ 191 mcr p15, 0, r0, c8, c7, 0 192 .endm 193 194 .macro write_tlbiallis 195 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 196 mcr p15, 0, r0, c8, c3, 0 197 .endm 198 199 .macro write_tlbiasidis reg 200 /* Invalidate unified TLB by ASID Inner Sharable */ 201 mcr p15, 0, \reg, c8, c3, 2 202 .endm 203 204 .macro write_tlbimvaais reg 205 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 206 mcr p15, 0, \reg, c8, c3, 3 207 .endm 208 209 .macro write_prrr reg 210 mcr p15, 0, \reg, c10, c2, 0 211 .endm 212 213 .macro read_prrr reg 214 mrc p15, 0, \reg, c10, c2, 0 215 .endm 216 217 .macro write_nmrr reg 218 mcr p15, 0, \reg, c10, c2, 1 219 .endm 220 221 .macro read_nmrr reg 222 mrc p15, 0, \reg, c10, c2, 1 223 .endm 224 225 .macro read_vbar reg 226 mrc p15, 0, \reg, c12, c0, 0 227 .endm 228 229 .macro write_vbar reg 230 mcr p15, 0, \reg, c12, c0, 0 231 .endm 232 233 .macro write_mvbar reg 234 mcr p15, 0, \reg, c12, c0, 1 235 .endm 236 237 .macro read_mvbar reg 238 mrc p15, 0, \reg, c12, c0, 1 239 .endm 240 241 .macro write_fcseidr reg 242 mcr p15, 0, \reg, c13, c0, 0 243 .endm 244 245 .macro read_fcseidr reg 246 mrc p15, 0, \reg, c13, c0, 0 247 .endm 248 249 .macro write_contextidr reg 250 mcr p15, 0, \reg, c13, c0, 1 251 .endm 252 253 .macro read_contextidr reg 254 mrc p15, 0, \reg, c13, c0, 1 255 .endm 256 257 .macro write_tpidruro reg 258 mcr p15, 0, \reg, c13, c0, 3 259 .endm 260 261 .macro read_tpidruro reg 262 mrc p15, 0, \reg, c13, c0, 3 263 .endm 264 265 .macro write_tpidrprw reg 266 mcr p15, 0, \reg, c13, c0, 4 267 .endm 268 269 .macro read_tpidrprw reg 270 mrc p15, 0, \reg, c13, c0, 4 271 .endm 272 273 .macro read_clidr reg 274 /* Cache Level ID Register */ 275 mrc p15, 1, \reg, c0, c0, 1 276 .endm 277 278 .macro read_ccsidr reg 279 /* Cache Size ID Registers */ 280 mrc p15, 1, \reg, c0, c0, 0 281 .endm 282 283 .macro write_csselr reg 284 /* Cache Size Selection Register */ 285 mcr p15, 2, \reg, c0, c0, 0 286 .endm 287 288 .macro mov_imm reg, val 289 .if ((\val) & 0xffff0000) == 0 290 movw \reg, #(\val) 291 .else 292 movw \reg, #((\val) & 0xffff) 293 movt \reg, #((\val) >> 16) 294 .endif 295 .endm 296 297