1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm32.h> 32 #include <console.h> 33 #include <drivers/gic.h> 34 #include <drivers/imx_uart.h> 35 #include <io.h> 36 #include <kernel/generic_boot.h> 37 #include <kernel/misc.h> 38 #include <kernel/panic.h> 39 #include <kernel/pm_stubs.h> 40 #include <mm/core_mmu.h> 41 #include <mm/core_memprot.h> 42 #include <platform_config.h> 43 #include <stdint.h> 44 #include <sm/optee_smc.h> 45 #include <tee/entry_fast.h> 46 #include <tee/entry_std.h> 47 48 49 static void main_fiq(void); 50 static struct gic_data gic_data; 51 52 static const struct thread_handlers handlers = { 53 .std_smc = tee_entry_std, 54 .fast_smc = tee_entry_fast, 55 .nintr = main_fiq, 56 .cpu_on = pm_panic, 57 .cpu_off = pm_panic, 58 .cpu_suspend = pm_panic, 59 .cpu_resume = pm_panic, 60 .system_off = pm_panic, 61 .system_reset = pm_panic, 62 }; 63 64 static struct imx_uart_data console_data; 65 66 #ifdef CONSOLE_UART_BASE 67 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, CORE_MMU_DEVICE_SIZE); 68 #endif 69 #ifdef GIC_BASE 70 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_DEVICE_SIZE); 71 #endif 72 #ifdef ANATOP_BASE 73 register_phys_mem(MEM_AREA_IO_SEC, ANATOP_BASE, CORE_MMU_DEVICE_SIZE); 74 #endif 75 #ifdef GICD_BASE 76 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, 0x10000); 77 #endif 78 #ifdef AIPS1_BASE 79 register_phys_mem(MEM_AREA_IO_SEC, AIPS1_BASE, 80 ROUNDUP(AIPS1_SIZE, CORE_MMU_DEVICE_SIZE)); 81 #endif 82 #ifdef AIPS2_BASE 83 register_phys_mem(MEM_AREA_IO_SEC, AIPS2_BASE, 84 ROUNDUP(AIPS2_SIZE, CORE_MMU_DEVICE_SIZE)); 85 #endif 86 #ifdef AIPS3_BASE 87 register_phys_mem(MEM_AREA_IO_SEC, AIPS3_BASE, 88 ROUNDUP(AIPS3_SIZE, CORE_MMU_DEVICE_SIZE)); 89 #endif 90 #ifdef IRAM_BASE 91 register_phys_mem(MEM_AREA_TEE_COHERENT, 92 ROUNDDOWN(IRAM_BASE, CORE_MMU_DEVICE_SIZE), 93 CORE_MMU_DEVICE_SIZE); 94 #endif 95 #ifdef IRAM_S_BASE 96 register_phys_mem(MEM_AREA_TEE_COHERENT, 97 ROUNDDOWN(IRAM_S_BASE, CORE_MMU_DEVICE_SIZE), 98 CORE_MMU_DEVICE_SIZE); 99 #endif 100 101 #if defined(CFG_PL310) 102 register_phys_mem(MEM_AREA_IO_SEC, 103 ROUNDDOWN(PL310_BASE, CORE_MMU_DEVICE_SIZE), 104 CORE_MMU_DEVICE_SIZE); 105 #endif 106 107 const struct thread_handlers *generic_boot_get_handlers(void) 108 { 109 return &handlers; 110 } 111 112 static void main_fiq(void) 113 { 114 gic_it_handle(&gic_data); 115 } 116 117 void console_init(void) 118 { 119 imx_uart_init(&console_data, CONSOLE_UART_BASE); 120 register_serial_console(&console_data.chip); 121 } 122 123 void main_init_gic(void) 124 { 125 vaddr_t gicc_base; 126 vaddr_t gicd_base; 127 128 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 129 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 130 131 if (!gicc_base || !gicd_base) 132 panic(); 133 134 /* Initialize GIC */ 135 gic_init(&gic_data, gicc_base, gicd_base); 136 itr_init(&gic_data.chip); 137 } 138 139 #if defined(CFG_MX6Q) || defined(CFG_MX6D) || defined(CFG_MX6DL) || \ 140 defined(CFG_MX7) 141 void main_secondary_init_gic(void) 142 { 143 gic_cpu_init(&gic_data); 144 } 145 #endif 146