1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * Copyright (c) 2015, Linaro Limited 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <mm/core_memprot.h> 31 #include <mm/core_mmu.h> 32 #include <tee/cache.h> 33 34 /* 35 * tee_uta_cache_operation - dynamic cache clean/inval request from a TA. 36 * It follows ARM recommendation: 37 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246d/Beicdhde.html 38 * Note that this implementation assumes dsb operations are part of 39 * cache_op_inner(), and outer cache sync are part of cache_op_outer(). 40 */ 41 TEE_Result cache_operation(enum utee_cache_operation op, void *va, size_t len) 42 { 43 TEE_Result res; 44 paddr_t pa; 45 46 pa = virt_to_phys(va); 47 if (!pa) 48 return TEE_ERROR_ACCESS_DENIED; 49 50 switch (op) { 51 case TEE_CACHEFLUSH: 52 #ifdef CFG_PL310 /* prevent initial L1 clean in case there is no outer L2 */ 53 /* Clean L1, Flush L2, Flush L1 */ 54 res = cache_op_inner(DCACHE_AREA_CLEAN, va, len); 55 if (res != TEE_SUCCESS) 56 return res; 57 res = cache_op_outer(DCACHE_AREA_CLEAN_INV, pa, len); 58 if (res != TEE_SUCCESS) 59 return res; 60 #endif 61 return cache_op_inner(DCACHE_AREA_CLEAN_INV, va, len); 62 63 case TEE_CACHECLEAN: 64 /* Clean L1, Clean L2 */ 65 res = cache_op_inner(DCACHE_AREA_CLEAN, va, len); 66 if (res != TEE_SUCCESS) 67 return res; 68 return cache_op_outer(DCACHE_AREA_CLEAN, pa, len); 69 70 case TEE_CACHEINVALIDATE: 71 /* Inval L2, Inval L1 */ 72 res = cache_op_outer(DCACHE_AREA_INVALIDATE, pa, len); 73 if (res != TEE_SUCCESS) 74 return res; 75 return cache_op_inner(DCACHE_AREA_INVALIDATE, va, len); 76 77 default: 78 return TEE_ERROR_NOT_SUPPORTED; 79 } 80 } 81