1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2016-2017, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <arm32_macros.S> 31#include <arm.h> 32#include <asm-defines.h> 33#include <asm.S> 34#include <keep.h> 35#include <kernel/abort.h> 36#include <kernel/thread_defs.h> 37#include <kernel/unwind.h> 38#include <mm/core_mmu.h> 39#include <sm/optee_smc.h> 40#include <sm/teesmc_opteed.h> 41#include <sm/teesmc_opteed_macros.h> 42 43#include "thread_private.h" 44 45 .macro cmp_spsr_user_mode reg:req 46 /* 47 * We're only testing the lower 4 bits as bit 5 (0x10) 48 * always is set. 49 */ 50 tst \reg, #0x0f 51 .endm 52 53LOCAL_FUNC vector_std_smc_entry , : 54UNWIND( .fnstart) 55UNWIND( .cantunwind) 56 push {r0-r7} 57 mov r0, sp 58 bl thread_handle_std_smc 59 /* 60 * Normally thread_handle_std_smc() should return via 61 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 62 * hasn't switched stack (error detected) it will do a normal "C" 63 * return. 64 */ 65 pop {r1-r8} 66 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 67 smc #0 68 b . /* SMC should not return */ 69UNWIND( .fnend) 70END_FUNC vector_std_smc_entry 71 72LOCAL_FUNC vector_fast_smc_entry , : 73UNWIND( .fnstart) 74UNWIND( .cantunwind) 75 push {r0-r7} 76 mov r0, sp 77 bl thread_handle_fast_smc 78 pop {r1-r8} 79 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 80 smc #0 81 b . /* SMC should not return */ 82UNWIND( .fnend) 83END_FUNC vector_fast_smc_entry 84 85LOCAL_FUNC vector_fiq_entry , : 86UNWIND( .fnstart) 87UNWIND( .cantunwind) 88 /* Secure Monitor received a FIQ and passed control to us. */ 89 bl thread_check_canaries 90 ldr lr, =thread_nintr_handler_ptr 91 ldr lr, [lr] 92 blx lr 93 mov r1, r0 94 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE 95 smc #0 96 b . /* SMC should not return */ 97UNWIND( .fnend) 98END_FUNC vector_fiq_entry 99 100LOCAL_FUNC vector_cpu_on_entry , : 101UNWIND( .fnstart) 102UNWIND( .cantunwind) 103 ldr lr, =thread_cpu_on_handler_ptr 104 ldr lr, [lr] 105 blx lr 106 mov r1, r0 107 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE 108 smc #0 109 b . /* SMC should not return */ 110UNWIND( .fnend) 111END_FUNC vector_cpu_on_entry 112 113LOCAL_FUNC vector_cpu_off_entry , : 114UNWIND( .fnstart) 115UNWIND( .cantunwind) 116 ldr lr, =thread_cpu_off_handler_ptr 117 ldr lr, [lr] 118 blx lr 119 mov r1, r0 120 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE 121 smc #0 122 b . /* SMC should not return */ 123UNWIND( .fnend) 124END_FUNC vector_cpu_off_entry 125 126LOCAL_FUNC vector_cpu_suspend_entry , : 127UNWIND( .fnstart) 128UNWIND( .cantunwind) 129 ldr lr, =thread_cpu_suspend_handler_ptr 130 ldr lr, [lr] 131 blx lr 132 mov r1, r0 133 ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 134 smc #0 135 b . /* SMC should not return */ 136UNWIND( .fnend) 137END_FUNC vector_cpu_suspend_entry 138 139LOCAL_FUNC vector_cpu_resume_entry , : 140UNWIND( .fnstart) 141UNWIND( .cantunwind) 142 ldr lr, =thread_cpu_resume_handler_ptr 143 ldr lr, [lr] 144 blx lr 145 mov r1, r0 146 ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE 147 smc #0 148 b . /* SMC should not return */ 149UNWIND( .fnend) 150END_FUNC vector_cpu_resume_entry 151 152LOCAL_FUNC vector_system_off_entry , : 153UNWIND( .fnstart) 154UNWIND( .cantunwind) 155 ldr lr, =thread_system_off_handler_ptr 156 ldr lr, [lr] 157 blx lr 158 mov r1, r0 159 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 160 smc #0 161 b . /* SMC should not return */ 162UNWIND( .fnend) 163END_FUNC vector_system_off_entry 164 165LOCAL_FUNC vector_system_reset_entry , : 166UNWIND( .fnstart) 167UNWIND( .cantunwind) 168 ldr lr, =thread_system_reset_handler_ptr 169 ldr lr, [lr] 170 blx lr 171 mov r1, r0 172 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 173 smc #0 174 b . /* SMC should not return */ 175UNWIND( .fnend) 176END_FUNC vector_system_reset_entry 177 178/* 179 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 180 * initialization. Also used when compiled with the internal monitor, but 181 * the cpu_*_entry and system_*_entry are not used then. 182 * 183 * Note that ARM-TF depends on the layout of this vector table, any change 184 * in layout has to be synced with ARM-TF. 185 */ 186FUNC thread_vector_table , : 187UNWIND( .fnstart) 188UNWIND( .cantunwind) 189 b vector_std_smc_entry 190 b vector_fast_smc_entry 191 b vector_cpu_on_entry 192 b vector_cpu_off_entry 193 b vector_cpu_resume_entry 194 b vector_cpu_suspend_entry 195 b vector_fiq_entry 196 b vector_system_off_entry 197 b vector_system_reset_entry 198UNWIND( .fnend) 199END_FUNC thread_vector_table 200KEEP_PAGER thread_vector_table 201 202FUNC thread_set_abt_sp , : 203UNWIND( .fnstart) 204UNWIND( .cantunwind) 205 mrs r1, cpsr 206 cps #CPSR_MODE_ABT 207 mov sp, r0 208 msr cpsr, r1 209 bx lr 210UNWIND( .fnend) 211END_FUNC thread_set_abt_sp 212 213FUNC thread_set_und_sp , : 214UNWIND( .fnstart) 215UNWIND( .cantunwind) 216 mrs r1, cpsr 217 cps #CPSR_MODE_UND 218 mov sp, r0 219 msr cpsr, r1 220 bx lr 221UNWIND( .fnend) 222END_FUNC thread_set_und_sp 223 224FUNC thread_set_irq_sp , : 225UNWIND( .fnstart) 226UNWIND( .cantunwind) 227 mrs r1, cpsr 228 cps #CPSR_MODE_IRQ 229 mov sp, r0 230 msr cpsr, r1 231 bx lr 232UNWIND( .fnend) 233END_FUNC thread_set_irq_sp 234 235FUNC thread_set_fiq_sp , : 236UNWIND( .fnstart) 237UNWIND( .cantunwind) 238 mrs r1, cpsr 239 cps #CPSR_MODE_FIQ 240 mov sp, r0 241 msr cpsr, r1 242 bx lr 243UNWIND( .fnend) 244END_FUNC thread_set_fiq_sp 245 246/* void thread_resume(struct thread_ctx_regs *regs) */ 247FUNC thread_resume , : 248UNWIND( .fnstart) 249UNWIND( .cantunwind) 250 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ 251 252 cps #CPSR_MODE_SYS 253 ldm r12!, {sp, lr} 254 255 cps #CPSR_MODE_SVC 256 ldm r12!, {r1, sp, lr} 257 msr spsr_fsxc, r1 258 259 ldm r12, {r1, r2} 260 261 /* 262 * Switching to some other mode than SVC as we need to set spsr in 263 * order to return into the old state properly and it may be SVC 264 * mode we're returning to. 265 */ 266 cps #CPSR_MODE_ABT 267 cmp_spsr_user_mode r2 268 mov lr, r1 269 msr spsr_fsxc, r2 270 ldm r0, {r0-r12} 271 movnes pc, lr 272 b eret_to_user_mode 273UNWIND( .fnend) 274END_FUNC thread_resume 275 276/* 277 * Disables IRQ and FIQ and saves state of thread in fiq mode which has 278 * the banked r8-r12 registers, returns original CPSR. 279 */ 280LOCAL_FUNC thread_save_state_fiq , : 281UNWIND( .fnstart) 282UNWIND( .cantunwind) 283 mov r9, lr 284 285 /* 286 * Uses stack for temporary storage, while storing needed 287 * context in the thread context struct. 288 */ 289 290 mrs r8, cpsr 291 292 cpsid aif /* Disable Async abort, IRQ and FIQ */ 293 294 push {r4-r7} 295 push {r0-r3} 296 297 mrs r6, cpsr /* Save current CPSR */ 298 299 bl thread_get_ctx_regs 300 301 pop {r1-r4} /* r0-r3 pushed above */ 302 stm r0!, {r1-r4} 303 pop {r1-r4} /* r4-r7 pushed above */ 304 stm r0!, {r1-r4} 305 306 cps #CPSR_MODE_SYS 307 stm r0!, {r8-r12} 308 stm r0!, {sp, lr} 309 310 cps #CPSR_MODE_SVC 311 mrs r1, spsr 312 stm r0!, {r1, sp, lr} 313 314 /* back to fiq mode */ 315 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 316 msr cpsr, r6 /* Restore mode */ 317 318 mov r0, r8 /* Return original CPSR */ 319 bx r9 320UNWIND( .fnend) 321END_FUNC thread_save_state_fiq 322 323/* 324 * Disables IRQ and FIQ and saves state of thread, returns original 325 * CPSR. 326 */ 327LOCAL_FUNC thread_save_state , : 328UNWIND( .fnstart) 329UNWIND( .cantunwind) 330 push {r12, lr} 331 /* 332 * Uses stack for temporary storage, while storing needed 333 * context in the thread context struct. 334 */ 335 336 mrs r12, cpsr 337 338 cpsid aif /* Disable Async abort, IRQ and FIQ */ 339 340 push {r4-r7} 341 push {r0-r3} 342 343 mov r5, r12 /* Save CPSR in a preserved register */ 344 mrs r6, cpsr /* Save current CPSR */ 345 346 bl thread_get_ctx_regs 347 348 pop {r1-r4} /* r0-r3 pushed above */ 349 stm r0!, {r1-r4} 350 pop {r1-r4} /* r4-r7 pushed above */ 351 stm r0!, {r1-r4} 352 stm r0!, {r8-r11} 353 354 pop {r12, lr} 355 stm r0!, {r12} 356 357 cps #CPSR_MODE_SYS 358 stm r0!, {sp, lr} 359 360 cps #CPSR_MODE_SVC 361 mrs r1, spsr 362 stm r0!, {r1, sp, lr} 363 364 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 365 msr cpsr, r6 /* Restore mode */ 366 367 mov r0, r5 /* Return original CPSR */ 368 bx lr 369UNWIND( .fnend) 370END_FUNC thread_save_state 371 372FUNC thread_std_smc_entry , : 373UNWIND( .fnstart) 374UNWIND( .cantunwind) 375 /* Pass r0-r7 in a struct thread_smc_args */ 376 push {r0-r7} 377 mov r0, sp 378 bl __thread_std_smc_entry 379 /* 380 * Load the returned r0-r3 into preserved registers and skip the 381 * "returned" r4-r7 since they will not be returned to normal 382 * world. 383 */ 384 pop {r4-r7} 385 add sp, #(4 * 4) 386 387 /* Disable interrupts before switching to temporary stack */ 388 cpsid aif 389 bl thread_get_tmp_sp 390 mov sp, r0 391 392 bl thread_state_free 393 394 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 395 mov r1, r4 396 mov r2, r5 397 mov r3, r6 398 mov r4, r7 399 smc #0 400 b . /* SMC should not return */ 401UNWIND( .fnend) 402END_FUNC thread_std_smc_entry 403 404 405/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 406FUNC thread_rpc , : 407/* 408 * r0-r2 are used to pass parameters to normal world 409 * r0-r5 are used to pass return vaule back from normal world 410 * 411 * note that r3 is used to pass "resume information", that is, which 412 * thread it is that should resume. 413 * 414 * Since the this function is following AAPCS we need to preserve r4-r5 415 * which are otherwise modified when returning back from normal world. 416 */ 417UNWIND( .fnstart) 418 push {r4-r5, lr} 419UNWIND( .save {r4-r5, lr}) 420 push {r0} 421UNWIND( .save {r0}) 422 423 bl thread_save_state 424 mov r4, r0 /* Save original CPSR */ 425 426 /* 427 * Switch to temporary stack and SVC mode. Save CPSR to resume into. 428 */ 429 bl thread_get_tmp_sp 430 ldr r5, [sp] /* Get pointer to rv[] */ 431 cps #CPSR_MODE_SVC /* Change to SVC mode */ 432 mov sp, r0 /* Switch to tmp stack */ 433 434 mov r0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 435 mov r1, r4 /* CPSR to restore */ 436 ldr r2, =.thread_rpc_return 437 bl thread_state_suspend 438 mov r4, r0 /* Supply thread index */ 439 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 440 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */ 441 smc #0 442 b . /* SMC should not return */ 443 444.thread_rpc_return: 445 /* 446 * At this point has the stack pointer been restored to the value 447 * it had when thread_save_state() was called above. 448 * 449 * Jumps here from thread_resume above when RPC has returned. The 450 * IRQ and FIQ bits are restored to what they where when this 451 * function was originally entered. 452 */ 453 pop {r12} /* Get pointer to rv[] */ 454 stm r12, {r0-r5} /* Store r0-r5 into rv[] */ 455 pop {r4-r5, pc} 456UNWIND( .fnend) 457END_FUNC thread_rpc 458KEEP_PAGER thread_rpc 459 460FUNC thread_init_vbar , : 461UNWIND( .fnstart) 462 /* Set vector (VBAR) */ 463 ldr r0, =thread_vect_table 464 write_vbar r0 465 bx lr 466UNWIND( .fnend) 467END_FUNC thread_init_vbar 468KEEP_PAGER thread_init_vbar 469 470/* 471 * Below are low level routines handling entry and return from user mode. 472 * 473 * thread_enter_user_mode() saves all that registers user mode can change 474 * so kernel mode can restore needed registers when resuming execution 475 * after the call to thread_enter_user_mode() has returned. 476 * thread_enter_user_mode() doesn't return directly since it enters user 477 * mode instead, it's thread_unwind_user_mode() that does the 478 * returning by restoring the registers saved by thread_enter_user_mode(). 479 * 480 * There's three ways for thread_enter_user_mode() to return to caller, 481 * user TA calls utee_return, user TA calls utee_panic or through an abort. 482 * 483 * Calls to utee_return or utee_panic are handled as: 484 * thread_svc_handler() -> tee_svc_handler() -> tee_svc_do_call() which 485 * calls syscall_return() or syscall_panic(). 486 * 487 * These function calls returns normally except thread_svc_handler() which 488 * which is an exception handling routine so it reads return address and 489 * SPSR to restore from the stack. syscall_return() and syscall_panic() 490 * changes return address and SPSR used by thread_svc_handler() to instead of 491 * returning into user mode as with other syscalls it returns into 492 * thread_unwind_user_mode() in kernel mode instead. When 493 * thread_svc_handler() returns the stack pointer at the point where 494 * thread_enter_user_mode() left it so this is where 495 * thread_unwind_user_mode() can operate. 496 * 497 * Aborts are handled in a similar way but by thread_abort_handler() 498 * instead, when the pager sees that it's an abort from user mode that 499 * can't be handled it updates SPSR and return address used by 500 * thread_abort_handler() to return into thread_unwind_user_mode() 501 * instead. 502 */ 503 504/* 505 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 506 * unsigned long a2, unsigned long a3, unsigned long user_sp, 507 * unsigned long user_func, unsigned long spsr, 508 * uint32_t *exit_status0, uint32_t *exit_status1) 509 * 510 */ 511FUNC __thread_enter_user_mode , : 512UNWIND( .fnstart) 513UNWIND( .cantunwind) 514 /* 515 * Save all registers to allow syscall_return() to resume execution 516 * as if this function would have returned. This is also used in 517 * syscall_panic(). 518 * 519 * If stack usage of this function is changed 520 * thread_unwind_user_mode() has to be updated. 521 */ 522 push {r4-r12,lr} 523 524 ldr r4, [sp, #(10 * 0x4)] /* user stack pointer */ 525 ldr r5, [sp, #(11 * 0x4)] /* user function */ 526 ldr r6, [sp, #(12 * 0x4)] /* spsr */ 527 528 /* 529 * Save old user sp and set new user sp. 530 */ 531 cps #CPSR_MODE_SYS 532 mov r7, sp 533 mov sp, r4 534 cps #CPSR_MODE_SVC 535 push {r7,r8} 536 537 /* Prepare user mode entry via eret_to_user_mode */ 538 cpsid aif 539 cps #CPSR_MODE_ABT 540 msr spsr_fsxc, r6 541 mov lr, r5 542 543 b eret_to_user_mode 544UNWIND( .fnend) 545END_FUNC __thread_enter_user_mode 546 547/* 548 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 549 * uint32_t exit_status1); 550 * See description in thread.h 551 */ 552FUNC thread_unwind_user_mode , : 553UNWIND( .fnstart) 554UNWIND( .cantunwind) 555 ldr ip, [sp, #(15 * 0x4)] /* &ctx->panicked */ 556 str r1, [ip] 557 ldr ip, [sp, #(16 * 0x4)] /* &ctx->panic_code */ 558 str r2, [ip] 559 560 /* Restore old user sp */ 561 pop {r4,r7} 562 cps #CPSR_MODE_SYS 563 mov sp, r4 564 cps #CPSR_MODE_SVC 565 566 pop {r4-r12,pc} /* Match the push in thread_enter_user_mode()*/ 567UNWIND( .fnend) 568END_FUNC thread_unwind_user_mode 569 570 .macro maybe_restore_mapping 571 /* 572 * This macro is a bit hard to read due to all the ifdefs, 573 * we're testing for two different configs which makes four 574 * different combinations. 575 * 576 * - With LPAE, and then some extra code if with 577 * CFG_CORE_UNMAP_CORE_AT_EL0 578 * - Without LPAE, and then some extra code if with 579 * CFG_CORE_UNMAP_CORE_AT_EL0 580 */ 581 582 /* 583 * At this point we can't rely on any memory being writable 584 * yet, so we're using TPIDRPRW to store r0, and if with 585 * LPAE TPIDRURO to store r1 too. 586 */ 587 write_tpidrprw r0 588 589#ifdef CFG_WITH_LPAE 590 write_tpidruro r1 591 592 read_ttbr0_64bit r0, r1 593 tst r1, #BIT(TTBR_ASID_SHIFT - 32) 594 beq 11f 595 596#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 597 /* 598 * Update the mapping to use the full kernel mode mapping. 599 * Since the translation table could reside above 4GB we'll 600 * have to use 64-bit arithmetics. 601 */ 602 subs r0, r0, #CORE_MMU_L1_TBL_OFFSET 603 sbc r1, r1, #0 604#endif 605 bic r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 606 write_ttbr0_64bit r0, r1 607 isb 608 609#else /*!CFG_WITH_LPAE*/ 610 read_contextidr r0 611 tst r0, #1 612 beq 11f 613 614 /* Update the mapping to use the full kernel mode mapping. */ 615 bic r0, r0, #1 616 write_contextidr r0 617 isb 618#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 619 read_ttbr1 r0 620 sub r0, r0, #CORE_MMU_L1_TBL_OFFSET 621 write_ttbr1 r0 622 isb 623#endif 624 625#endif /*!CFG_WITH_LPAE*/ 626 627#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 628 ldr r0, =thread_vect_table 629 write_vbar r0 630 isb 631 632 11: /* 633 * The PC is adjusted unconditionally to guard against the 634 * case there was an FIQ just before we did the "cpsid aif". 635 */ 636 ldr r0, =22f 637 bx r0 638 22: 639#else 640 11: 641#endif 642 read_tpidrprw r0 643#ifdef CFG_WITH_LPAE 644 read_tpidruro r1 645#endif 646 .endm 647 648/* The handler of native interrupt. */ 649.macro native_intr_handler mode:req 650 cpsid aif 651 maybe_restore_mapping 652 653 /* 654 * FIQ and IRQ have a +4 offset for lr compared to preferred return 655 * address 656 */ 657 sub lr, lr, #4 658 659 /* 660 * We're always saving {r0-r3}. In IRQ mode we're saving r12 also. 661 * In FIQ mode we're saving the banked fiq registers {r8-r12} FIQ 662 * because the secure monitor doesn't save those. The treatment of 663 * the banked fiq registers is somewhat analogous to the lazy save 664 * of VFP registers. 665 */ 666 push {r0-r3} 667 .ifc \mode\(),fiq 668 push {r8-r12, lr} 669 .else 670 push {r12, lr} 671 .endif 672 673 bl thread_check_canaries 674 ldr lr, =thread_nintr_handler_ptr 675 ldr lr, [lr] 676 blx lr 677 678 .ifc \mode\(),fiq 679 pop {r8-r12, lr} 680 .else 681 pop {r12, lr} 682 .endif 683 684 mov r0, sp 685 mrs r1, spsr 686 mov r2, lr 687 add sp, sp, #(4 * 4) 688 cps #CPSR_MODE_ABT 689 cmp_spsr_user_mode r1 690 msr spsr_fsxc, r1 691 mov lr, r2 692 ldm r0, {r0-r3} 693 movnes pc, lr 694 b eret_to_user_mode 695.endm 696 697/* The handler of foreign interrupt. */ 698.macro foreign_intr_handler mode:req 699 cpsid aif 700 maybe_restore_mapping 701 702 sub lr, lr, #4 703 push {lr} 704 push {r12} 705 706 .ifc \mode\(),fiq 707 bl thread_save_state_fiq 708 .else 709 bl thread_save_state 710 .endif 711 712 mov r0, #THREAD_FLAGS_EXIT_ON_FOREIGN_INTR 713 mrs r1, spsr 714 pop {r12} 715 pop {r2} 716 blx thread_state_suspend 717 mov r4, r0 /* Supply thread index */ 718 719 /* 720 * Switch to SVC mode and copy current stack pointer as it already 721 * is the tmp stack. 722 */ 723 mov r0, sp 724 cps #CPSR_MODE_SVC 725 mov sp, r0 726 727 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 728 ldr r1, =OPTEE_SMC_RETURN_RPC_FOREIGN_INTR 729 mov r2, #0 730 mov r3, #0 731 /* r4 is already filled in above */ 732 smc #0 733 b . /* SMC should not return */ 734.endm 735 736 .section .text.thread_vect_table 737 .align 5 738FUNC thread_vect_table , : 739UNWIND( .fnstart) 740UNWIND( .cantunwind) 741 b . /* Reset */ 742 b thread_und_handler /* Undefined instruction */ 743 b thread_svc_handler /* System call */ 744 b thread_pabort_handler /* Prefetch abort */ 745 b thread_dabort_handler /* Data abort */ 746 b . /* Reserved */ 747 b thread_irq_handler /* IRQ */ 748 b thread_fiq_handler /* FIQ */ 749 750thread_und_handler: 751 cpsid aif 752 maybe_restore_mapping 753 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 754 mrs r1, spsr 755 tst r1, #CPSR_T 756 subne lr, lr, #2 757 subeq lr, lr, #4 758 mov r0, #ABORT_TYPE_UNDEF 759 b thread_abort_common 760 761thread_dabort_handler: 762 cpsid aif 763 maybe_restore_mapping 764 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 765 sub lr, lr, #8 766 mov r0, #ABORT_TYPE_DATA 767 b thread_abort_common 768 769thread_pabort_handler: 770 cpsid aif 771 maybe_restore_mapping 772 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 773 sub lr, lr, #4 774 mov r0, #ABORT_TYPE_PREFETCH 775 776thread_abort_common: 777 /* 778 * At this label: 779 * cpsr is in mode undef or abort 780 * sp is still pointing to struct thread_core_local belonging to 781 * this core. 782 * {r0, r1} are saved in struct thread_core_local pointed to by sp 783 * {r2-r11, ip} are untouched. 784 * r0 holds the first argument for abort_handler() 785 */ 786 787 /* 788 * Update core local flags. 789 * flags = (flags << THREAD_CLF_SAVED_SHIFT) | THREAD_CLF_ABORT; 790 */ 791 ldr r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 792 lsl r1, r1, #THREAD_CLF_SAVED_SHIFT 793 orr r1, r1, #THREAD_CLF_ABORT 794 795 /* 796 * Select stack and update flags accordingly 797 * 798 * Normal case: 799 * If the abort stack is unused select that. 800 * 801 * Fatal error handling: 802 * If we're already using the abort stack as noted by bit 803 * (THREAD_CLF_SAVED_SHIFT + THREAD_CLF_ABORT_SHIFT) in the flags 804 * field we're selecting the temporary stack instead to be able to 805 * make a stack trace of the abort in abort mode. 806 * 807 * r1 is initialized as a temporary stack pointer until we've 808 * switched to system mode. 809 */ 810 tst r1, #(THREAD_CLF_ABORT << THREAD_CLF_SAVED_SHIFT) 811 orrne r1, r1, #THREAD_CLF_TMP /* flags |= THREAD_CLF_TMP; */ 812 str r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 813 ldrne r1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 814 ldreq r1, [sp, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 815 816 /* 817 * Store registers on stack fitting struct thread_abort_regs 818 * start from the end of the struct 819 * {r2-r11, ip} 820 * Load content of previously saved {r0-r1} and stores 821 * it up to the pad field. 822 * After this is only {usr_sp, usr_lr} missing in the struct 823 */ 824 stmdb r1!, {r2-r11, ip} /* Push on the selected stack */ 825 ldrd r2, r3, [sp, #THREAD_CORE_LOCAL_R0] 826 /* Push the original {r0-r1} on the selected stack */ 827 stmdb r1!, {r2-r3} 828 mrs r3, spsr 829 /* Push {pad, spsr, elr} on the selected stack */ 830 stmdb r1!, {r2, r3, lr} 831 832 cps #CPSR_MODE_SYS 833 str lr, [r1, #-4]! 834 str sp, [r1, #-4]! 835 mov sp, r1 836 837 bl abort_handler 838 839 mov ip, sp 840 ldr sp, [ip], #4 841 ldr lr, [ip], #4 842 843 /* 844 * Even if we entered via CPSR_MODE_UND, we are returning via 845 * CPSR_MODE_ABT. It doesn't matter as lr and spsr are assigned 846 * here. 847 */ 848 cps #CPSR_MODE_ABT 849 ldm ip!, {r0, r1, lr} /* r0 is pad */ 850 msr spsr_fsxc, r1 851 852 /* Update core local flags */ 853 ldr r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 854 lsr r0, r0, #THREAD_CLF_SAVED_SHIFT 855 str r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 856 857 cmp_spsr_user_mode r1 858 ldm ip, {r0-r11, ip} 859 movnes pc, lr 860 b eret_to_user_mode 861 /* end thread_abort_common */ 862 863thread_svc_handler: 864 cpsid aif 865 866 maybe_restore_mapping 867 868 push {r0-r7, lr} 869 mrs r0, spsr 870 push {r0} 871 mov r0, sp 872 bl tee_svc_handler 873 cpsid aif /* In case something was unmasked */ 874 /* Use ip instead of stack pointer as we need to switch mode. */ 875 mov ip, sp 876 add sp, #(4 * 10) 877 cps #CPSR_MODE_ABT 878 ldr r0, [ip], #4 879 msr spsr_fsxc, r0 880 cmp_spsr_user_mode r0 881 ldm ip, {r0-r7, lr} 882 movnes pc, lr 883 b eret_to_user_mode 884 /* end thread_svc_handler */ 885 886thread_fiq_handler: 887#if defined(CFG_ARM_GICV3) 888 foreign_intr_handler fiq 889#else 890 native_intr_handler fiq 891#endif 892 /* end thread_fiq_handler */ 893 894thread_irq_handler: 895#if defined(CFG_ARM_GICV3) 896 native_intr_handler irq 897#else 898 foreign_intr_handler irq 899#endif 900 /* end thread_irq_handler */ 901 902 /* 903 * Returns to user mode. 904 * Expects to be jumped to with lr pointing to the user space 905 * address to jump to and spsr holding the desired cpsr. Async 906 * abort, irq and fiq should be masked. 907 */ 908eret_to_user_mode: 909 write_tpidrprw r0 910#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 911 write_tpidruro r1 912#endif 913 914#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 915 ldr r0, =thread_user_kcode_offset 916 ldr r0, [r0] 917 adr r1, thread_vect_table 918 sub r1, r1, r0 919 write_vbar r1 920 isb 921 922 /* Jump into the reduced mapping before the full mapping is removed */ 923 ldr r1, =1f 924 sub r1, r1, r0 925 bx r1 9261: 927#endif /*CFG_CORE_UNMAP_CORE_AT_EL0*/ 928 929#ifdef CFG_WITH_LPAE 930 read_ttbr0_64bit r0, r1 931#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 932 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 933#endif 934 /* switch to user ASID */ 935 orr r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 936 write_ttbr0_64bit r0, r1 937 isb 938#else /*!CFG_WITH_LPAE*/ 939#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 940 read_ttbr1 r0 941 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 942 write_ttbr1 r0 943 isb 944#endif 945 read_contextidr r0 946 orr r0, r0, #BIT(0) 947 write_contextidr r0 948 isb 949#endif /*!CFG_WITH_LPAE*/ 950 951 read_tpidrprw r0 952#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 953 read_tpidruro r1 954#endif 955 956 movs pc, lr 957UNWIND( .fnend) 958END_FUNC thread_vect_table 959