1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 6 #include <console.h> 7 #include <drivers/pl011.h> 8 #ifdef CFG_SPI 9 #include <drivers/pl022_spi.h> 10 #include <drivers/pl061_gpio.h> 11 #endif 12 #if defined(PLATFORM_FLAVOR_hikey) 13 #include <hikey_peripherals.h> 14 #endif 15 #include <initcall.h> 16 #include <io.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/pm_stubs.h> 20 #include <mm/tee_pager.h> 21 #include <mm/core_memprot.h> 22 #include <platform_config.h> 23 #include <stdint.h> 24 #include <tee/entry_std.h> 25 #include <tee/entry_fast.h> 26 27 static void main_fiq(void); 28 29 static const struct thread_handlers handlers = { 30 .std_smc = tee_entry_std, 31 .fast_smc = tee_entry_fast, 32 .nintr = main_fiq, 33 .cpu_on = cpu_on_handler, 34 .cpu_off = pm_do_nothing, 35 .cpu_suspend = pm_do_nothing, 36 .cpu_resume = pm_do_nothing, 37 .system_off = pm_do_nothing, 38 .system_reset = pm_do_nothing, 39 }; 40 41 static struct pl011_data console_data; 42 43 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 44 #if defined(PLATFORM_FLAVOR_hikey) 45 register_phys_mem(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 46 #endif 47 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 48 register_phys_mem(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 49 register_phys_mem(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 50 register_phys_mem(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 51 register_phys_mem(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 52 register_phys_mem(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 53 #endif 54 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE_NSEC); 55 56 const struct thread_handlers *generic_boot_get_handlers(void) 57 { 58 return &handlers; 59 } 60 61 static void main_fiq(void) 62 { 63 panic(); 64 } 65 66 void console_init(void) 67 { 68 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 69 CONSOLE_BAUDRATE); 70 register_serial_console(&console_data.chip); 71 } 72 73 #if defined(PLATFORM_FLAVOR_hikey) 74 #ifdef CFG_SPI 75 void spi_init(void) 76 { 77 uint32_t shifted_val, read_val; 78 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 79 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 80 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 81 82 DMSG("take SPI0 out of reset\n"); 83 shifted_val = PERI_RST3_SSP; 84 /* 85 * no need to read PERI_SC_PERIPH_RSTDIS3 first 86 * as all the bits are processed and cleared after writing 87 */ 88 write32(shifted_val, peri_base + PERI_SC_PERIPH_RSTDIS3); 89 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 90 read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 91 92 /* 93 * wait until the requested device is out of reset 94 * and ready to be used 95 */ 96 do { 97 read_val = read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 98 } while (read_val & shifted_val); 99 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 100 101 DMSG("enable SPI clock\n"); 102 /* 103 * no need to read PERI_SC_PERIPH_CLKEN3 first 104 * as all the bits are processed and cleared after writing 105 */ 106 shifted_val = PERI_CLK3_SSP; 107 write32(shifted_val, peri_base + PERI_SC_PERIPH_CLKEN3); 108 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 109 read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 110 111 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 112 read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 113 114 /* 115 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 116 * will control the chip select pin so we don't have to manually do it. 117 * The only concern is that the IP will pulse it between each packet, 118 * which might not work with certain clients. There seems to be no 119 * option to configure it to stay enabled for the total duration of the 120 * transfer. 121 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 122 */ 123 DMSG("configure gpio6 pins 0-3 as SPI\n"); 124 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG104); 125 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG105); 126 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG106); 127 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG107); 128 129 DMSG("configure gpio6 pins 0-3 as nopull\n"); 130 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG104); 131 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG105); 132 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG106); 133 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG107); 134 135 #ifdef CFG_SPI_TEST 136 spi_test(); 137 #endif 138 } 139 #endif 140 141 static TEE_Result peripherals_init(void) 142 { 143 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 144 145 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 146 /* 147 * Mezzanine cards usually use this to source level shifters for 148 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 149 * peripherals will not work either (during bootloader stage) 150 * until linux is booted. 151 */ 152 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 153 PMUSSI_LDO21_REG_VL_MASK); 154 write8(PMUSSI_ENA_LDO21, pmussi_base + PMUSSI_ENA_LDO17_22); 155 156 #ifdef CFG_SPI 157 spi_init(); 158 #endif 159 return TEE_SUCCESS; 160 } 161 162 driver_init(peripherals_init); 163 #endif /* PLATFORM_FLAVOR_hikey */ 164