core: lsp: add RAS error injection logical secure partition

Add a Logical Secure Partition (LSP) that handles FF-A direct requests
for RAS error injection.

The LSP programs the CPU RAS Error Record

core: lsp: add RAS error injection logical secure partition

Add a Logical Secure Partition (LSP) that handles FF-A direct requests
for RAS error injection.

The LSP programs the CPU RAS Error Record and PFG registers
for the requested injection type and returns the programming status
to the caller.

Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: add RAS register access helpers

Add primitive arm64 register access helpers for the RAS Error Record
and PFG registers used by the RAS injection LSP.

This allows the register programming

core: arm: add RAS register access helpers

Add primitive arm64 register access helpers for the RAS Error Record
and PFG registers used by the RAS injection LSP.

This allows the register programming to be done from C
without separate assembly helper functions.

Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: route SP direct requests to logical secure partitions

Extend the SPMC direct request handling so Logical Secure Partitions
(LSPs) can receive direct requests in addition to regular SPs.

core: spmc: route SP direct requests to logical secure partitions

Extend the SPMC direct request handling so Logical Secure Partitions
(LSPs) can receive direct requests in addition to regular SPs.

This updates the LSP direct_req() callback to take caller_sp, allowing
the handler to distinguish requests coming from an SP from those coming
through the normal-world path. The SPMC direct request flow is updated to
look up LSP destinations, validate their direct request properties, and
route matching requests to the registered LSP callback.

The test LSP callback is updated accordingly.

Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: move endpoint ID helpers to ffa.h

Move the FFA_DST() and FFA_SRC() endpoint ID helper macros
to ffa.h, which is the common FF-A header.

This makes the helpers available from the generic

core: ffa: move endpoint ID helpers to ffa.h

Move the FFA_DST() and FFA_SRC() endpoint ID helper macros
to ffa.h, which is the common FF-A header.

This makes the helpers available from the generic FF-A interface
instead of keeping them in spmc_sp_handler.h, and removes
the duplicate local definitions from that header.

Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-qcom: enable PAS early TA when PTA is enabled

The TA contains platform-independent authentication logic, but it
depends on the PAS PTA for the platform-specific operations needed to
act on the

plat-qcom: enable PAS early TA when PTA is enabled

The TA contains platform-independent authentication logic, but it
depends on the PAS PTA for the platform-specific operations needed to
act on the firmware image.

Restricting the TA to platforms that provide the PTA avoids enabling a
non-functional configuration.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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pta: qcom: pas: map PAS resources on demand

Stop registering PAS-related IO regions at platform initialization
time and instead map them on demand when the PAS PTA is initialized.

The WPSS, TURING,

pta: qcom: pas: map PAS resources on demand

Stop registering PAS-related IO regions at platform initialization
time and instead map them on demand when the PAS PTA is initialized.

The WPSS, TURING, LPASS and IRIS regions were previously mapped
statically via register_phys_mem(). These mappings are now removed
and the PAS controller region is mapped dynamically using
core_mmu_add_mapping() when the PTA performs the memory setup.

Since PAS resources are now mapped late, increase
CFG_RESERVED_VASPACE_SIZE to ensure sufficient virtual address
space is available.

This change reduces permanent IO mappings and keeps PAS resources
localized to the PTA implementation.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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pta: qcom_pas: Add support for Venus

Add Peripheral Authentication Service (PAS) support for the
Venus video codec, enabling firmware loading through the
existing remoteproc integration.

Firmware a

pta: qcom_pas: Add support for Venus

Add Peripheral Authentication Service (PAS) support for the
Venus video codec, enabling firmware loading through the
existing remoteproc integration.

Firmware authentication is not implemented at this stage.

Execution has been validated by running concurrent video
encode and decode workloads using a GStreamer pipeline.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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pta: qcom_pas: Add support for ADSP

Add Peripheral Authentication Service (PAS) support for the
Audio DSP (ADSP), enabling loading of the ADSP firmware image.

Authentication not done yet.

Initial

pta: qcom_pas: Add support for ADSP

Add Peripheral Authentication Service (PAS) support for the
Audio DSP (ADSP), enabling loading of the ADSP firmware image.

Authentication not done yet.

Initial validation used https://github.com/qualcomm/fastrpc.git
(all tests pass)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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pta: qcom_pas: Add support for CDSP

Add Peripheral Authentication Service (PAS) support for the
Compute DSP (CDSP), enabling loading of the CDSP firmware image.

Authentication not done yet.

Initia

pta: qcom_pas: Add support for CDSP

Add Peripheral Authentication Service (PAS) support for the
Compute DSP (CDSP), enabling loading of the CDSP firmware image.

Authentication not done yet.

Initial validation used https://github.com/qualcomm/fastrpc.git
(all tests pass)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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plat: qcom: kodiak: move clock definitions to platform header

Move Kodiak-specific GCC clock register offsets out of the generic
clock-qcom driver into a platform header.

Introduce clock_group_qcom

plat: qcom: kodiak: move clock definitions to platform header

Move Kodiak-specific GCC clock register offsets out of the generic
clock-qcom driver into a platform header.

Introduce clock_group_qcom.h under platform/kodiak to hold the clock
register offsets required by the driver and update the build system so
the platform include path is visible to the clock driver.

Also move the GCC MMIO mapping from plat-qcom/main.c into the clock
driver. This keeps the mapping local to the driver that consumes the
registers and avoids exposing platform clock registers globally during
platform initialization.

This change is a preparation step to support additional Qualcomm
platforms while keeping the common clock driver platform-agnostic.

No functional change intended.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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plat: qcom: kodiak: Enable PAS pseudo TA and WPSS bringup

Enable support for PAS pseudo TA along with functionality to bringup
WPSS co-processor.

Co-developed-by: Casey Connolly <casey.connolly@lin

plat: qcom: kodiak: Enable PAS pseudo TA and WPSS bringup

Enable support for PAS pseudo TA along with functionality to bringup
WPSS co-processor.

Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

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drivers: versal_net: Add OCP driver

On Versal NET devices (only) PLM Firmware has a module called XilOCP,
providing services related to the Open Compute Project (OCP) security
standards (PCR handlin

drivers: versal_net: Add OCP driver

On Versal NET devices (only) PLM Firmware has a module called XilOCP,
providing services related to the Open Compute Project (OCP) security
standards (PCR handling, Device Management Endorsement, Attestation).

This commit adds functions which are more or less equivalent to the XilOCP
client side API offers.

Since most Versal and Versal NET drivers more or less re-implement rather
similar handling of struct versal_ipi_cmd, this commit also adds and hereby
proposes a new set of helper functions for commonly used operations on
struct versal_ipi_cmd. With these versal_ipi_cmd_*() functions data
words ("Values") and "IPI buffers" can easily be "pushed" onto a struct
versal_ipi_cmd.

For now, only this OCP driver makes use of these versal_ipi_cmd_*()
functions. Thus they have been placed directly in versal_ocp.c instead of
having them located in a separate drivers/ file, like
drivers/versal_ipi_cmd.c [1].

Link: https://github.com/OP-TEE/optee_os/pull/7726#issuecomment-4237954478 [1]
Signed-off-by: Dennis Ries <dennis.ries@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

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drivers: versal_net: trng: Add support for newer PKI TRNG and use in PKI driver

The TRNG IP Core included in Versal NET PKI Accelerator is close to Versal
PMC TRNG IP Core but includes hardware DF a

drivers: versal_net: trng: Add support for newer PKI TRNG and use in PKI driver

The TRNG IP Core included in Versal NET PKI Accelerator is close to Versal
PMC TRNG IP Core but includes hardware DF and can be called a 2nd version
of that IP Core.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com> and
huynhdanvo <dan.vo@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal_net: trng: Add support for TRNG via PLM Firmware

In contrast to Versal, the PMC TRNG IP is driven by the PLM Firmware
exclusively, since the latter is also using it.

Largely based o

drivers: versal_net: trng: Add support for TRNG via PLM Firmware

In contrast to Versal, the PMC TRNG IP is driven by the PLM Firmware
exclusively, since the latter is also using it.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

plat-versal: Increase IPI command timeout

On Versal and Versal NET certain PLM IPI commands require more time to
complete. Tests showed that for RSA-4096 decryption not even 150ms do
suffice on Vers

plat-versal: Increase IPI command timeout

On Versal and Versal NET certain PLM IPI commands require more time to
complete. Tests showed that for RSA-4096 decryption not even 150ms do
suffice on Versal NET. Thus we move to 200 ms, for now.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>

show more ...

plat-versal: Add support for Versal NET variant

Versal NET is a new SoC flavor based on the Versal architecture.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

plat-versal: Add support for Versal NET variant

Versal NET is a new SoC flavor based on the Versal architecture.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

drivers: versal: mbox: Rework

- Offer a generic IPI/Mailbox API in versal_mbox.c and ...
- ... provide the default IPI channel to the PMC for other drivers in
versal_pmc.c .

- Improve performance

drivers: versal: mbox: Rework

- Offer a generic IPI/Mailbox API in versal_mbox.c and ...
- ... provide the default IPI channel to the PMC for other drivers in
versal_pmc.c .

- Improve performance by doing notification by direct, memory-mapped
register access instead of doing it through the SecureMonitor.

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

plat-versal: Increase TEE memory and heap size to 512k / 4M

To be able to use the Versal Loader PTA with at least rather minimal FPGA
bitstreams (as subsystem PDI files) for demonstration purposes a

plat-versal: Increase TEE memory and heap size to 512k / 4M

To be able to use the Versal Loader PTA with at least rather minimal FPGA
bitstreams (as subsystem PDI files) for demonstration purposes a little
more than 256k of heap is needed. Thus we double it to 512k. Doubling the
total amount of virtual memory from the default of 2M (ARMv8) seems to be
reasonable then.

Since boards with Versal devices usually do not have too little DDR RAM,
doubling these default settings shall not be general issue.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

core: pta: versal: Add loader PTA

Simple PTA allowing to dynamically load subsystem PDI files into the Versal
device, using the versal_pm.c driver, which is in turn using the PLM
XilLoader module, A

core: pta: versal: Add loader PTA

Simple PTA allowing to dynamically load subsystem PDI files into the Versal
device, using the versal_pm.c driver, which is in turn using the PLM
XilLoader module, API id 0x0701 (LOAD_SUBSYSTEM_PDI).

Largely based on previous work by
Jeremie Corbier <jeremie.corbier@provenrun.com>.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

plat-versal: Add flavors uart1 and net_uart1 to select UART1 instead of UART0

Some Versal boards, like Trenz TE0950 use the 2nd UART peripheral instead
of the 1st UART peripheral exclusively. Now, c

plat-versal: Add flavors uart1 and net_uart1 to select UART1 instead of UART0

Some Versal boards, like Trenz TE0950 use the 2nd UART peripheral instead
of the 1st UART peripheral exclusively. Now, compile-time argument
PLATFORM=versal-uart1 (or PLATFORM=versal-net_uart1) can be used to cover
these situations.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

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plat-versal: Decrease default amount of static shared memory to 128MiB

It turns that reserving 256MiB at 0x70000000 in Linux is not possible at
least with AMD/Xilinx Linux v2024.2, since various oth

plat-versal: Decrease default amount of static shared memory to 128MiB

It turns that reserving 256MiB at 0x70000000 in Linux is not possible at
least with AMD/Xilinx Linux v2024.2, since various other higher-prio
reservations seem to be present beyond 0x78000000 on a typical Versal
system:

78fa3000-78faafff : reserved
78fad000-79ea1fff : reserved
7c000000-7fffffff : reserved

Note that 0x78000000 is the start of the last 128MiB on DRAM Memory
Controller 0, Region 0 (lower 2 GiB). Further DRAM is mapped starting at
0x800000000, way beyond 4GiB.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Reviewed-by: Nathan Menhorn <nathan.menhorn@amd.com>
Tested-by: Nathan Menhorn <nathan.menhorn@amd.com>
Reviewed-by: Sean McGinn <sean.mcginn@amd.com>
Reviewed-by: Lucas Kiker <lucas.kiker@amd.com>
Reviewed-by: Sindhu Raveendra <Sindhu.Raveendra@amd.com>
Reviewed-by: Clemens Nasenberg <clemens.nasenberg@amd.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

show more ...

plat-bcm: support the tracing feature on all consoles.

Decouple the tracing configuration from the console type so that tracing
remains available when any other console type is configured.

Signed-o

plat-bcm: support the tracing feature on all consoles.

Decouple the tracing configuration from the console type so that tracing
remains available when any other console type is configured.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-altera: introduce SoCFPGA platform support

Add initial support for the SoCFPGA platform under plat/altera.

This commit introduces the basic platform skeleton, including build
configuration, pl

plat-altera: introduce SoCFPGA platform support

Add initial support for the SoCFPGA platform under plat/altera.

This commit introduces the basic platform skeleton, including build
configuration, platform initialization entry points, and configuration
headers required for bring-up.

Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: fix memory range tracking in mobj_ffa_add_pages_at()

In mobj_ffa_add_pages_at(), the PA check for protected memory checked
the wrong offset and idx was incremented by the wrong variable.

core: ffa: fix memory range tracking in mobj_ffa_add_pages_at()

In mobj_ffa_add_pages_at(), the PA check for protected memory checked
the wrong offset and idx was incremented by the wrong variable. Fix both
for correct validation.

Fixes: 003383344c26 ("core: support dynamic protected memory lending")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>

show more ...

core: ffa: fix double indexing in get_acc_perms()

With OP-TEE configured as SPMC with CFG_CORE_SEL1_SPMC=y,
get_acc_perms() is used to get the offset of a struct ffa_mem_region
descriptor.

The mem_

core: ffa: fix double indexing in get_acc_perms()

With OP-TEE configured as SPMC with CFG_CORE_SEL1_SPMC=y,
get_acc_perms() is used to get the offset of a struct ffa_mem_region
descriptor.

The mem_acc pointer is already advanced to the correct element via
stride calculation. So remove the incorrect index to read region_offs
from the correct memory location.

Fixes: a1c53023cc80 ("core: spmc: support FF-A 1.1")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>

show more ...