plat: qcom: add platform banner

Display a basic platform banner.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-b

plat: qcom: add platform banner

Display a basic platform banner.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Tony Hamilton <tonyh@qti.qualcomm.com>

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drivers: qcom: prng: add PRNG driver

The Qualcomm PRNG hardware generates cryptographic keys and random
numbers.

The PRNG is configured by the first-stage bootloader. This includes the
reseed frequ

drivers: qcom: prng: add PRNG driver

The Qualcomm PRNG hardware generates cryptographic keys and random
numbers.

The PRNG is configured by the first-stage bootloader. This includes the
reseed frequency.

This driver only consumes the generated output.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Tony Hamilton <tonyh@qti.qualcomm.com>

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drivers: qcom: ramblur: configure pIMEM access

Configure memory access to enable execution of Trusted Applications.

OP-TEE and its Trusted Applications execute from pIMEM, a region protected
by the

drivers: qcom: ramblur: configure pIMEM access

Configure memory access to enable execution of Trusted Applications.

OP-TEE and its Trusted Applications execute from pIMEM, a region protected
by the RAMBLUR IP block.

RAMBLUR provides anti-rollback protection as well as confidentiality and
integrity guarantees for the memory region under its control.

Any agent accessing the pIMEM-protected region performs normal reads or
writes to the pIMEM address range in the SNoC. The SNoC routes these
transactions to the pIMEM slave port, and pIMEM remasters them to DDR.

For write transactions, pIMEM applies the required cryptographic
operations before committing data to DDR.

For read transactions, pIMEM applies the corresponding cryptographic
operations before returning the data from DDR to the requesting master.

The reserved DDR region used by pIMEM to store cryptographically
processed data and associated cryptographic state is referred to as the
pIMEM vault.

With the current U-Boot (tag 2026.01-rc3), the pIMEM Vault DDR
reservation is derived from the TZ node in U-Boot’s built-in device tree
(specifically the trusted_apps_mem reserved-memory node).

U-Boot uses this node to construct the EFI memory map that is later
passed to the kernel.

A future update will remove this dependency on the built-in device tree.
Instead, U-Boot will obtain the memory configuration directly from SMEM.
Because of this transition, the current version of the driver does not
generate a DT overlay for U-Boot to consume.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Tony Hamilton <tonyh@qti.qualcomm.com>

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plat-rockchip: rk3588: assert buffer is size of HUK

The size of the buffer that is used to persist the HUK in the OTP and
the size of the buffer that is used to read the HUK from the OTP must
have t

plat-rockchip: rk3588: assert buffer is size of HUK

The size of the buffer that is used to persist the HUK in the OTP and
the size of the buffer that is used to read the HUK from the OTP must
have the same size as the HUK key data.

Add a static_assert to ensure that this is actually the case.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-corstone1000: Add Cortex-A320 support

Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the

plat-corstone1000: Add Cortex-A320 support

Convert arm64-platform-cpuarch from a hard-coded cortex-a35 into a “?=”
(default) assignment so users can override it (for example to
cortex-a320) via the make command line.

The Cortex-A320 core is not yet supported via -mcpu=cortex-a320.
When arm64-platform-cpuarch is set to cortex-a320, switch to
-march=armv9.2-a.

The new Corstone-1000 variant with Cortex-A320 replaces the original
GIC-400 (v2) interrupt controller with a GIC-600, which is
architecturally compliant with GICv3. Since OP-TEE already provides
a generic GICv3 driver, only minimal platform changes are needed
to expose the updated register map and initialize the GICv3 interface.

**Changes introduced**

* When `cortex-a320` is selected:
* Force `CFG_ARM_GICV3=y`.
* Map the Redistributor region (`GICR_BASE`).
* Use `gic_init_v3(…)` instead of the v2 helper for Cortex-A320 builds.
* Add `GICR_BASE`, `GIC_REDIST_REG_SIZE`, and related offsets.
* Retain legacy `GICC_BASE` definitions under the GICv2 path so that
the Cortex-A35 + GIC-400 variant continues to build unchanged.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Add support for TI mailbox driver

New devices like the AM62L use a mailbox to communicate with the
security firmware. Add mailbox driver here to support the mailbox
hardware.

Sign

plat-k3: drivers: Add support for TI mailbox driver

New devices like the AM62L use a mailbox to communicate with the
security firmware. Add mailbox driver here to support the mailbox
hardware.

Signed-off-by: Aniket Sarkar <a-sarkar1@ti.com>
Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Refactor sec_proxy driver

Since the underneath transport layer may or may not always be sec_proxy
it doesn't make sense to keep following the k3_sec_proxy_* convention
for the TI_S

plat-k3: drivers: Refactor sec_proxy driver

Since the underneath transport layer may or may not always be sec_proxy
it doesn't make sense to keep following the k3_sec_proxy_* convention
for the TI_SCI message transports.
Rename them to something more generic like ti_sci_transport_*.

Signed-off-by: Aniket Sarkar <a-sarkar1@ti.com>
Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Set SEC_PROXY_MAX_MSG_SIZE to 56

Currently, SEC_PROXY_MAX_MSG_SIZE is set to 60. However, its max size
(including the secure header) is 56. Therefore correct this macro.

Signed-of

plat-k3: drivers: Set SEC_PROXY_MAX_MSG_SIZE to 56

Currently, SEC_PROXY_MAX_MSG_SIZE is set to 60. However, its max size
(including the secure header) is 56. Therefore correct this macro.

Signed-off-by: Suhaas Joshi <s-joshi@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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plat-k3: drivers: Open TRNG firewall for TIFS on all k3 devs

On k3 devices, TRNG is firewalled to be accessed only by OPTEE.

TIFS needs this for the encryption and decryption services to support
di

plat-k3: drivers: Open TRNG firewall for TIFS on all k3 devs

On k3 devices, TRNG is firewalled to be accessed only by OPTEE.

TIFS needs this for the encryption and decryption services to support
different low power modes. So, open firewall to TIFS as well.

There is no concurrent usage of TRNG, as TIFS uses TRNG only at suspend
when OPTEE is down and resume, when firewalls are restored but OPTEE is
not up yet.

As this is a firewall that required to be shared along with TIFS on all
devices, making this a common change and open on all devs.

Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>

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core: ffa: add missing field in memory access descriptor

FF-A v1.2 introduced a 16 byte implementation-defined field in the
endpoint memory access descriptor. Update all handling of struct
ffa_mem_a

core: ffa: add missing field in memory access descriptor

FF-A v1.2 introduced a 16 byte implementation-defined field in the
endpoint memory access descriptor. Update all handling of struct
ffa_mem_access to for correct access regardless of FF-A version.

With this patch, OP-TEE will use the updated memory access descriptor,
but ignore the impdef field.

Suggested-by: Olivier Deprez <olivier.deprez@arm.com>
Fixes: bef959c837fe ("core: arm: ffa: switch to FF-A version 1.2")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: enable MU and ELE driver on i.MX943

Enable MU and ELE driver on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>

core: imx: enable MU and ELE driver on i.MX943

Enable MU and ELE driver on i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add MU_BASE and MU_SIZE for i.MX943

Add MU_BASE and MU_SIZE for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>

core: imx: add MU_BASE and MU_SIZE for i.MX943

Add MU_BASE and MU_SIZE for i.MX943

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add support for i.MX943 EVK

Add support for i.MX943 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens W

core: imx: add support for i.MX943 EVK

Add support for i.MX943 EVK

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add i.MX943 SoC ID

Add i.MX943 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wik

core: imx: add i.MX943 SoC ID

Add i.MX943 SoC ID

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add i.MX943 registers

Add i.MX943 registers

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <je

core: imx: add i.MX943 registers

Add i.MX943 registers

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: increase thread stack size with KASAN/check-stacks

Increase STACK_THREAD_SIZE from 10 KiB to 12 KiB when
CFG_CORE_SANITIZE_KADDRESS is enabled.

With the previous size, some regression

core: arm64: increase thread stack size with KASAN/check-stacks

Increase STACK_THREAD_SIZE from 10 KiB to 12 KiB when
CFG_CORE_SANITIZE_KADDRESS is enabled.

With the previous size, some regression tests (for example
regression_1006 "Test Basic OS features") may fail due to stack
canary corruption caused by the additional stack usage from
instrumentation.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp2: conf: default enable CFG_STM32_I2C for stm32mp2 family

Default enable STM32 I2C driver on STM32MP2 platforms.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by

plat-stm32mp2: conf: default enable CFG_STM32_I2C for stm32mp2 family

Default enable STM32 I2C driver on STM32MP2 platforms.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add i2c1 to i2c3 nodes in stm32mp211.dtsi

The STM32MP23x has a total of 3 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.c

dts: stm32: add i2c1 to i2c3 nodes in stm32mp211.dtsi

The STM32MP23x has a total of 3 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add i2c1, i2c2, i2c7 and i2c8 nodes in stm32mp231.dtsi

The STM32MP23x has a total of 4 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourg

dts: stm32: add i2c1, i2c2, i2c7 and i2c8 nodes in stm32mp231.dtsi

The STM32MP23x has a total of 4 instances of I2C.
Add all of them in stm32mp231.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add i2c1 to i2c8 nodes in stm32mp251.dtsi

The STM32MP25x has a total of 8 instances of I2C hence add all
of them in stm32mp251.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss

dts: stm32: add i2c1 to i2c8 nodes in stm32mp251.dtsi

The STM32MP25x has a total of 8 instances of I2C hence add all
of them in stm32mp251.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-ti: Fix initialisation order

Since commit 358cdcd2b079 ("core: arm32: initialize secure monitor
late") TI platforms have been broken due to only initialising the
HUK in `init_sec_mon` after the

plat-ti: Fix initialisation order

Since commit 358cdcd2b079 ("core: arm32: initialize secure monitor
late") TI platforms have been broken due to only initialising the
HUK in `init_sec_mon` after the SSK has been derived/generated from
it in the `tee_fs_init_key_manager` service init.

Move initialisation of HUK into an `early_init` registration to
restore the correct order of operations.

Secure monitor initialisation cannot be moved into the
`early_init()` as the secure monitor stack is not yet initialised.

Link: https://github.com/OP-TEE/optee_os/issues/7587

Signed-off-by: Alistair Higgins <Alistair_Higgins@trimble.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-telechips: fix spelling mistake

Fix a spelling mistake in the tcmktool.py script.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@lina

plat-telechips: fix spelling mistake

Fix a spelling mistake in the tcmktool.py script.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: guard sp_session field state with spinlock

Accesses to the state field in struct sp_session is often guarded with a
spinlock, but there are a few places with it's missing. So, add the
mis

core: ffa: guard sp_session field state with spinlock

Accesses to the state field in struct sp_session is often guarded with a
spinlock, but there are a few places with it's missing. So, add the
missing spinlocks.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ffa: verify thread ID before resuming S-EL0 SP

Check that the thread ID for an S-EL0 SP is correct before trying to
resume it. This guards against resuming an unrelated thread.

Signed-off-by:

core: ffa: verify thread ID before resuming S-EL0 SP

Check that the thread ID for an S-EL0 SP is correct before trying to
resume it. This guards against resuming an unrelated thread.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ffa: fix direct request error code for S-EL0 SP

Direct requests to S-EL0 SPs are delivered using a thread. If no thread
is available return FFA_BUSY, to let the caller know that it should try

core: ffa: fix direct request error code for S-EL0 SP

Direct requests to S-EL0 SPs are delivered using a thread. If no thread
is available return FFA_BUSY, to let the caller know that it should try
again. This should normally never happen, but let's do our best for a
corner case.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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