1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #ifndef ARM_H 29 #define ARM_H 30 31 #include <util.h> 32 33 #define MPIDR_CPU_MASK 0xff 34 #define MPIDR_CLUSTER_SHIFT 8 35 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 36 37 38 /* CLIDR definitions */ 39 #define CLIDR_LOUIS_SHIFT 21 40 #define CLIDR_LOC_SHIFT 24 41 #define CLIDR_FIELD_WIDTH 3 42 43 /* CSSELR definitions */ 44 #define CSSELR_LEVEL_SHIFT 1 45 46 /* CTR definitions */ 47 #define CTR_CWG_SHIFT 24 48 #define CTR_CWG_MASK 0xf 49 #define CTR_ERG_SHIFT 20 50 #define CTR_ERG_MASK 0xf 51 #define CTR_DMINLINE_SHIFT 16 52 #define CTR_DMINLINE_WIDTH 4 53 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 54 #define CTR_L1IP_SHIFT 14 55 #define CTR_L1IP_MASK 0x3 56 #define CTR_IMINLINE_SHIFT 0 57 #define CTR_IMINLINE_MASK 0xf 58 59 #define ARM32_CPSR_MODE_MASK 0x1f 60 #define ARM32_CPSR_MODE_USR 0x10 61 #define ARM32_CPSR_MODE_FIQ 0x11 62 #define ARM32_CPSR_MODE_IRQ 0x12 63 #define ARM32_CPSR_MODE_SVC 0x13 64 #define ARM32_CPSR_MODE_MON 0x16 65 #define ARM32_CPSR_MODE_ABT 0x17 66 #define ARM32_CPSR_MODE_UND 0x1b 67 #define ARM32_CPSR_MODE_SYS 0x1f 68 69 #define ARM32_CPSR_T (1 << 5) 70 #define ARM32_CPSR_F_SHIFT 6 71 #define ARM32_CPSR_F (1 << 6) 72 #define ARM32_CPSR_I (1 << 7) 73 #define ARM32_CPSR_A (1 << 8) 74 #define ARM32_CPSR_E (1 << 9) 75 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 76 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 77 #define ARM32_CPSR_IT_MASK1 0x06000000 78 #define ARM32_CPSR_IT_MASK2 0x0000fc00 79 80 /* ARM Generic timer definitions */ 81 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 82 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 83 84 #ifdef ARM32 85 #include <arm32.h> 86 #endif 87 88 #ifdef ARM64 89 #include <arm64.h> 90 #endif 91 92 #endif /*ARM_H*/ 93