1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 */ 6 7 #include <console.h> 8 #include <drivers/pl011.h> 9 #ifdef CFG_SPI 10 #include <drivers/pl022_spi.h> 11 #include <drivers/pl061_gpio.h> 12 #endif 13 #if defined(PLATFORM_FLAVOR_hikey) 14 #include <hikey_peripherals.h> 15 #endif 16 #include <initcall.h> 17 #include <io.h> 18 #include <kernel/generic_boot.h> 19 #include <kernel/panic.h> 20 #include <kernel/pm_stubs.h> 21 #include <mm/tee_pager.h> 22 #include <mm/core_memprot.h> 23 #include <platform_config.h> 24 #include <stdint.h> 25 #include <tee/entry_std.h> 26 #include <tee/entry_fast.h> 27 28 static void main_fiq(void); 29 30 static const struct thread_handlers handlers = { 31 .std_smc = tee_entry_std, 32 .fast_smc = tee_entry_fast, 33 .nintr = main_fiq, 34 .cpu_on = cpu_on_handler, 35 .cpu_off = pm_do_nothing, 36 .cpu_suspend = pm_do_nothing, 37 .cpu_resume = pm_do_nothing, 38 .system_off = pm_do_nothing, 39 .system_reset = pm_do_nothing, 40 }; 41 42 static struct pl011_data console_data; 43 44 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 45 #if defined(PLATFORM_FLAVOR_hikey) 46 register_phys_mem(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE); 47 #endif 48 #if defined(CFG_SPI) && defined(PLATFORM_FLAVOR_hikey) 49 register_phys_mem(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE); 50 register_phys_mem(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE); 51 register_phys_mem(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE); 52 register_phys_mem(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE); 53 register_phys_mem(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE); 54 #endif 55 register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE_NSEC); 56 57 const struct thread_handlers *generic_boot_get_handlers(void) 58 { 59 return &handlers; 60 } 61 62 static void main_fiq(void) 63 { 64 panic(); 65 } 66 67 void console_init(void) 68 { 69 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 70 CONSOLE_BAUDRATE); 71 register_serial_console(&console_data.chip); 72 } 73 74 #if defined(PLATFORM_FLAVOR_hikey) 75 #ifdef CFG_SPI 76 void spi_init(void) 77 { 78 uint32_t shifted_val, read_val; 79 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC); 80 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC); 81 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC); 82 83 DMSG("take SPI0 out of reset\n"); 84 shifted_val = PERI_RST3_SSP; 85 /* 86 * no need to read PERI_SC_PERIPH_RSTDIS3 first 87 * as all the bits are processed and cleared after writing 88 */ 89 write32(shifted_val, peri_base + PERI_SC_PERIPH_RSTDIS3); 90 DMSG("PERI_SC_PERIPH_RSTDIS3: 0x%x\n", 91 read32(peri_base + PERI_SC_PERIPH_RSTDIS3)); 92 93 /* 94 * wait until the requested device is out of reset 95 * and ready to be used 96 */ 97 do { 98 read_val = read32(peri_base + PERI_SC_PERIPH_RSTSTAT3); 99 } while (read_val & shifted_val); 100 DMSG("PERI_SC_PERIPH_RSTSTAT3: 0x%x\n", read_val); 101 102 DMSG("enable SPI clock\n"); 103 /* 104 * no need to read PERI_SC_PERIPH_CLKEN3 first 105 * as all the bits are processed and cleared after writing 106 */ 107 shifted_val = PERI_CLK3_SSP; 108 write32(shifted_val, peri_base + PERI_SC_PERIPH_CLKEN3); 109 DMSG("PERI_SC_PERIPH_CLKEN3: 0x%x\n", 110 read32(peri_base + PERI_SC_PERIPH_CLKEN3)); 111 112 DMSG("PERI_SC_PERIPH_CLKSTAT3: 0x%x\n", 113 read32(peri_base + PERI_SC_PERIPH_CLKSTAT3)); 114 115 /* 116 * GPIO6_2 can be configured as PINMUX_GPIO, but as PINMUX_SPI, HW IP 117 * will control the chip select pin so we don't have to manually do it. 118 * The only concern is that the IP will pulse it between each packet, 119 * which might not work with certain clients. There seems to be no 120 * option to configure it to stay enabled for the total duration of the 121 * transfer. 122 * ref: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/CJACFAFG.html 123 */ 124 DMSG("configure gpio6 pins 0-3 as SPI\n"); 125 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG104); 126 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG105); 127 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG106); 128 write32(PINMUX_SPI, pmx0_base + PMX0_IOMG107); 129 130 DMSG("configure gpio6 pins 0-3 as nopull\n"); 131 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG104); 132 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG105); 133 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG106); 134 write32(PINCFG_NOPULL, pmx1_base + PMX1_IOCG107); 135 136 #ifdef CFG_SPI_TEST 137 spi_test(); 138 #endif 139 } 140 #endif 141 142 static TEE_Result peripherals_init(void) 143 { 144 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC); 145 146 DMSG("enable LD021_1V8 source (pin 35) on LS connector\n"); 147 /* 148 * Mezzanine cards usually use this to source level shifters for 149 * UART, GPIO, SPI, I2C, etc so if not enabled, connected 150 * peripherals will not work either (during bootloader stage) 151 * until linux is booted. 152 */ 153 io_mask8(pmussi_base + PMUSSI_LDO21_REG_ADJ, PMUSSI_LDO21_REG_VL_1V8, 154 PMUSSI_LDO21_REG_VL_MASK); 155 write8(PMUSSI_ENA_LDO21, pmussi_base + PMUSSI_ENA_LDO17_22); 156 157 #ifdef CFG_SPI 158 spi_init(); 159 #endif 160 return TEE_SUCCESS; 161 } 162 163 driver_init(peripherals_init); 164 #endif /* PLATFORM_FLAVOR_hikey */ 165