1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM_H 6 #define ARM_H 7 8 #include <util.h> 9 10 #define MPIDR_CPU_MASK 0xff 11 #define MPIDR_CLUSTER_SHIFT 8 12 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 13 14 15 /* CLIDR definitions */ 16 #define CLIDR_LOUIS_SHIFT 21 17 #define CLIDR_LOC_SHIFT 24 18 #define CLIDR_FIELD_WIDTH 3 19 20 /* CSSELR definitions */ 21 #define CSSELR_LEVEL_SHIFT 1 22 23 /* CTR definitions */ 24 #define CTR_CWG_SHIFT 24 25 #define CTR_CWG_MASK 0xf 26 #define CTR_ERG_SHIFT 20 27 #define CTR_ERG_MASK 0xf 28 #define CTR_DMINLINE_SHIFT 16 29 #define CTR_DMINLINE_WIDTH 4 30 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 31 #define CTR_L1IP_SHIFT 14 32 #define CTR_L1IP_MASK 0x3 33 #define CTR_IMINLINE_SHIFT 0 34 #define CTR_IMINLINE_MASK 0xf 35 36 #define ARM32_CPSR_MODE_MASK 0x1f 37 #define ARM32_CPSR_MODE_USR 0x10 38 #define ARM32_CPSR_MODE_FIQ 0x11 39 #define ARM32_CPSR_MODE_IRQ 0x12 40 #define ARM32_CPSR_MODE_SVC 0x13 41 #define ARM32_CPSR_MODE_MON 0x16 42 #define ARM32_CPSR_MODE_ABT 0x17 43 #define ARM32_CPSR_MODE_UND 0x1b 44 #define ARM32_CPSR_MODE_SYS 0x1f 45 46 #define ARM32_CPSR_T (1 << 5) 47 #define ARM32_CPSR_F_SHIFT 6 48 #define ARM32_CPSR_F (1 << 6) 49 #define ARM32_CPSR_I (1 << 7) 50 #define ARM32_CPSR_A (1 << 8) 51 #define ARM32_CPSR_E (1 << 9) 52 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 53 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 54 #define ARM32_CPSR_IT_MASK1 0x06000000 55 #define ARM32_CPSR_IT_MASK2 0x0000fc00 56 57 /* ARM Generic timer definitions */ 58 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 59 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 60 61 #ifdef ARM32 62 #include <arm32.h> 63 #endif 64 65 #ifdef ARM64 66 #include <arm64.h> 67 #endif 68 69 #endif /*ARM_H*/ 70