1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #ifndef ARM64_H 29 #define ARM64_H 30 31 #include <sys/cdefs.h> 32 #include <stdint.h> 33 #include <util.h> 34 35 #define SCTLR_M BIT32(0) 36 #define SCTLR_A BIT32(1) 37 #define SCTLR_C BIT32(2) 38 #define SCTLR_SA BIT32(3) 39 #define SCTLR_I BIT32(12) 40 #define SCTLR_WXN BIT32(19) 41 42 #define TTBR_ASID_MASK 0xff 43 #define TTBR_ASID_SHIFT 48 44 45 #define CLIDR_LOUIS_SHIFT 21 46 #define CLIDR_LOC_SHIFT 24 47 #define CLIDR_FIELD_WIDTH 3 48 49 #define CSSELR_LEVEL_SHIFT 1 50 51 #define DAIFBIT_FIQ BIT32(0) 52 #define DAIFBIT_IRQ BIT32(1) 53 #define DAIFBIT_ABT BIT32(2) 54 #define DAIFBIT_DBG BIT32(3) 55 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 56 DAIFBIT_ABT | DAIFBIT_DBG) 57 58 #define DAIF_F_SHIFT 6 59 #define DAIF_F BIT32(6) 60 #define DAIF_I BIT32(7) 61 #define DAIF_A BIT32(8) 62 #define DAIF_D BIT32(9) 63 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 64 65 #define SPSR_MODE_RW_SHIFT 4 66 #define SPSR_MODE_RW_MASK 0x1 67 #define SPSR_MODE_RW_64 0x0 68 #define SPSR_MODE_RW_32 0x1 69 70 #define SPSR_64_MODE_SP_SHIFT 0 71 #define SPSR_64_MODE_SP_MASK 0x1 72 #define SPSR_64_MODE_SP_EL0 0x0 73 #define SPSR_64_MODE_SP_ELX 0x1 74 75 #define SPSR_64_MODE_EL_SHIFT 2 76 #define SPSR_64_MODE_EL_MASK 0x3 77 #define SPSR_64_MODE_EL1 0x1 78 #define SPSR_64_MODE_EL0 0x0 79 80 #define SPSR_64_DAIF_SHIFT 6 81 #define SPSR_64_DAIF_MASK 0xf 82 83 #define SPSR_32_AIF_SHIFT 6 84 #define SPSR_32_AIF_MASK 0x7 85 86 #define SPSR_32_E_SHIFT 9 87 #define SPSR_32_E_MASK 0x1 88 #define SPSR_32_E_LITTLE 0x0 89 #define SPSR_32_E_BIG 0x1 90 91 #define SPSR_32_T_SHIFT 5 92 #define SPSR_32_T_MASK 0x1 93 #define SPSR_32_T_ARM 0x0 94 #define SPSR_32_T_THUMB 0x1 95 96 #define SPSR_32_MODE_SHIFT 0 97 #define SPSR_32_MODE_MASK 0xf 98 #define SPSR_32_MODE_USR 0x0 99 100 101 #define SPSR_64(el, sp, daif) \ 102 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 103 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 104 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 105 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 106 107 #define SPSR_32(mode, isa, aif) \ 108 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 109 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 110 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 111 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 112 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 113 114 115 #define TCR_T0SZ_SHIFT 0 116 #define TCR_EPD0 BIT32(7) 117 #define TCR_IRGN0_SHIFT 8 118 #define TCR_ORGN0_SHIFT 10 119 #define TCR_SH0_SHIFT 12 120 #define TCR_T1SZ_SHIFT 16 121 #define TCR_A1 BIT32(22) 122 #define TCR_EPD1 BIT32(23) 123 #define TCR_IRGN1_SHIFT 24 124 #define TCR_ORGN1_SHIFT 26 125 #define TCR_SH1_SHIFT 28 126 #define TCR_EL1_IPS_SHIFT 32 127 #define TCR_TG1_4KB SHIFT_U32(2, 30) 128 #define TCR_RES1 BIT32(31) 129 130 131 /* Normal memory, Inner/Outer Non-cacheable */ 132 #define TCR_XRGNX_NC 0x0 133 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 134 #define TCR_XRGNX_WB 0x1 135 /* Normal memory, Inner/Outer Write-Through Cacheable */ 136 #define TCR_XRGNX_WT 0x2 137 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 138 #define TCR_XRGNX_WBWA 0x3 139 140 /* Non-shareable */ 141 #define TCR_SHX_NSH 0x0 142 /* Outer Shareable */ 143 #define TCR_SHX_OSH 0x2 144 /* Inner Shareable */ 145 #define TCR_SHX_ISH 0x3 146 147 #define ESR_EC_SHIFT 26 148 #define ESR_EC_MASK 0x3f 149 150 #define ESR_EC_UNKNOWN 0x00 151 #define ESR_EC_WFI 0x01 152 #define ESR_EC_AARCH32_CP15_32 0x03 153 #define ESR_EC_AARCH32_CP15_64 0x04 154 #define ESR_EC_AARCH32_CP14_MR 0x05 155 #define ESR_EC_AARCH32_CP14_LS 0x06 156 #define ESR_EC_FP_ASIMD 0x07 157 #define ESR_EC_AARCH32_CP10_ID 0x08 158 #define ESR_EC_AARCH32_CP14_64 0x0c 159 #define ESR_EC_ILLEGAL 0x0e 160 #define ESR_EC_AARCH32_SVC 0x11 161 #define ESR_EC_AARCH64_SVC 0x15 162 #define ESR_EC_AARCH64_SYS 0x18 163 #define ESR_EC_IABT_EL0 0x20 164 #define ESR_EC_IABT_EL1 0x21 165 #define ESR_EC_PC_ALIGN 0x22 166 #define ESR_EC_DABT_EL0 0x24 167 #define ESR_EC_DABT_EL1 0x25 168 #define ESR_EC_SP_ALIGN 0x26 169 #define ESR_EC_AARCH32_FP 0x28 170 #define ESR_EC_AARCH64_FP 0x2c 171 #define ESR_EC_SERROR 0x2f 172 #define ESR_EC_BREAKPT_EL0 0x30 173 #define ESR_EC_BREAKPT_EL1 0x31 174 #define ESR_EC_SOFTSTP_EL0 0x32 175 #define ESR_EC_SOFTSTP_EL1 0x33 176 #define ESR_EC_WATCHPT_EL0 0x34 177 #define ESR_EC_WATCHPT_EL1 0x35 178 #define ESR_EC_AARCH32_BKPT 0x38 179 #define ESR_EC_AARCH64_BRK 0x3c 180 181 /* Combined defines for DFSC and IFSC */ 182 #define ESR_FSC_MASK 0x3f 183 #define ESR_FSC_SIZE_L0 0x00 184 #define ESR_FSC_SIZE_L1 0x01 185 #define ESR_FSC_SIZE_L2 0x02 186 #define ESR_FSC_SIZE_L3 0x03 187 #define ESR_FSC_TRANS_L0 0x04 188 #define ESR_FSC_TRANS_L1 0x05 189 #define ESR_FSC_TRANS_L2 0x06 190 #define ESR_FSC_TRANS_L3 0x07 191 #define ESR_FSC_ACCF_L1 0x09 192 #define ESR_FSC_ACCF_L2 0x0a 193 #define ESR_FSC_ACCF_L3 0x0b 194 #define ESR_FSC_PERMF_L1 0x0d 195 #define ESR_FSC_PERMF_L2 0x0e 196 #define ESR_FSC_PERMF_L3 0x0f 197 #define ESR_FSC_ALIGN 0x21 198 199 /* WnR for DABT and RES0 for IABT */ 200 #define ESR_ABT_WNR BIT32(6) 201 202 #define CPACR_EL1_FPEN_SHIFT 20 203 #define CPACR_EL1_FPEN_MASK 0x3 204 #define CPACR_EL1_FPEN_NONE 0x0 205 #define CPACR_EL1_FPEN_EL1 0x1 206 #define CPACR_EL1_FPEN_EL0EL1 0x3 207 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 208 & CPACR_EL1_FPEN_MASK) 209 210 211 #define PAR_F BIT32(0) 212 #define PAR_PA_SHIFT 12 213 #define PAR_PA_MASK (BIT64(36) - 1) 214 215 #define TLBI_MVA_SHIFT 12 216 #define TLBI_ASID_SHIFT 48 217 #define TLBI_ASID_MASK 0xff 218 219 #ifndef ASM 220 static inline void isb(void) 221 { 222 asm volatile ("isb"); 223 } 224 225 static inline void dsb(void) 226 { 227 asm volatile ("dsb sy"); 228 } 229 230 static inline void dsb_ish(void) 231 { 232 asm volatile ("dsb ish"); 233 } 234 235 static inline void dsb_ishst(void) 236 { 237 asm volatile ("dsb ishst"); 238 } 239 240 static inline void write_at_s1e1r(uint64_t va) 241 { 242 asm volatile ("at S1E1R, %0" : : "r" (va)); 243 } 244 245 static __always_inline uint64_t read_pc(void) 246 { 247 uint64_t val; 248 249 asm volatile ("adr %0, ." : "=r" (val)); 250 return val; 251 } 252 253 static __always_inline uint64_t read_fp(void) 254 { 255 uint64_t val; 256 257 asm volatile ("mov %0, x29" : "=r" (val)); 258 return val; 259 } 260 261 static inline uint64_t read_pmu_ccnt(void) 262 { 263 uint64_t val; 264 265 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 266 return val; 267 } 268 269 static inline void tlbi_vaae1is(uint64_t mva) 270 { 271 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 272 } 273 274 /* 275 * Templates for register read/write functions based on mrs/msr 276 */ 277 278 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 279 static inline type read_##reg(void) \ 280 { \ 281 type val; \ 282 \ 283 asm volatile("mrs %0, " #asmreg : "=r" (val)); \ 284 return val; \ 285 } 286 287 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 288 static inline void write_##reg(type val) \ 289 { \ 290 asm volatile("msr " #asmreg ", %0" : : "r" (val)); \ 291 } 292 293 #define DEFINE_U32_REG_READ_FUNC(reg) \ 294 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 295 296 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 297 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 298 299 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 300 DEFINE_U32_REG_READ_FUNC(reg) \ 301 DEFINE_U32_REG_WRITE_FUNC(reg) 302 303 #define DEFINE_U64_REG_READ_FUNC(reg) \ 304 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 305 306 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 307 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 308 309 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 310 DEFINE_U64_REG_READ_FUNC(reg) \ 311 DEFINE_U64_REG_WRITE_FUNC(reg) 312 313 /* 314 * Define register access functions 315 */ 316 317 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 318 DEFINE_U32_REG_READWRITE_FUNCS(daif) 319 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 320 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 321 322 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 323 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 324 325 /* ARM Generic timer functions */ 326 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 327 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 328 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 329 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 330 331 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 332 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 333 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 334 335 DEFINE_U64_REG_READ_FUNC(esr_el1) 336 DEFINE_U64_REG_READ_FUNC(far_el1) 337 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 338 DEFINE_U64_REG_READ_FUNC(par_el1) 339 340 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 341 342 /* Register read/write functions for GICC registers by using system interface */ 343 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 344 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 345 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 346 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 347 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 348 #endif /*ASM*/ 349 350 #endif /*ARM64_H*/ 351 352