1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 */ 6 #ifndef ARM64_H 7 #define ARM64_H 8 9 #include <sys/cdefs.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 #define SCTLR_M BIT32(0) 14 #define SCTLR_A BIT32(1) 15 #define SCTLR_C BIT32(2) 16 #define SCTLR_SA BIT32(3) 17 #define SCTLR_I BIT32(12) 18 #define SCTLR_WXN BIT32(19) 19 20 #define TTBR_ASID_MASK 0xff 21 #define TTBR_ASID_SHIFT 48 22 23 #define CLIDR_LOUIS_SHIFT 21 24 #define CLIDR_LOC_SHIFT 24 25 #define CLIDR_FIELD_WIDTH 3 26 27 #define CSSELR_LEVEL_SHIFT 1 28 29 #define DAIFBIT_FIQ BIT32(0) 30 #define DAIFBIT_IRQ BIT32(1) 31 #define DAIFBIT_ABT BIT32(2) 32 #define DAIFBIT_DBG BIT32(3) 33 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \ 34 DAIFBIT_ABT | DAIFBIT_DBG) 35 36 #define DAIF_F_SHIFT 6 37 #define DAIF_F BIT32(6) 38 #define DAIF_I BIT32(7) 39 #define DAIF_A BIT32(8) 40 #define DAIF_D BIT32(9) 41 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F) 42 43 #define SPSR_MODE_RW_SHIFT 4 44 #define SPSR_MODE_RW_MASK 0x1 45 #define SPSR_MODE_RW_64 0x0 46 #define SPSR_MODE_RW_32 0x1 47 48 #define SPSR_64_MODE_SP_SHIFT 0 49 #define SPSR_64_MODE_SP_MASK 0x1 50 #define SPSR_64_MODE_SP_EL0 0x0 51 #define SPSR_64_MODE_SP_ELX 0x1 52 53 #define SPSR_64_MODE_EL_SHIFT 2 54 #define SPSR_64_MODE_EL_MASK 0x3 55 #define SPSR_64_MODE_EL1 0x1 56 #define SPSR_64_MODE_EL0 0x0 57 58 #define SPSR_64_DAIF_SHIFT 6 59 #define SPSR_64_DAIF_MASK 0xf 60 61 #define SPSR_32_AIF_SHIFT 6 62 #define SPSR_32_AIF_MASK 0x7 63 64 #define SPSR_32_E_SHIFT 9 65 #define SPSR_32_E_MASK 0x1 66 #define SPSR_32_E_LITTLE 0x0 67 #define SPSR_32_E_BIG 0x1 68 69 #define SPSR_32_T_SHIFT 5 70 #define SPSR_32_T_MASK 0x1 71 #define SPSR_32_T_ARM 0x0 72 #define SPSR_32_T_THUMB 0x1 73 74 #define SPSR_32_MODE_SHIFT 0 75 #define SPSR_32_MODE_MASK 0xf 76 #define SPSR_32_MODE_USR 0x0 77 78 79 #define SPSR_64(el, sp, daif) \ 80 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \ 81 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \ 82 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \ 83 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT) 84 85 #define SPSR_32(mode, isa, aif) \ 86 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \ 87 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \ 88 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \ 89 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \ 90 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT) 91 92 93 #define TCR_T0SZ_SHIFT 0 94 #define TCR_EPD0 BIT32(7) 95 #define TCR_IRGN0_SHIFT 8 96 #define TCR_ORGN0_SHIFT 10 97 #define TCR_SH0_SHIFT 12 98 #define TCR_T1SZ_SHIFT 16 99 #define TCR_A1 BIT32(22) 100 #define TCR_EPD1 BIT32(23) 101 #define TCR_IRGN1_SHIFT 24 102 #define TCR_ORGN1_SHIFT 26 103 #define TCR_SH1_SHIFT 28 104 #define TCR_EL1_IPS_SHIFT 32 105 #define TCR_TG1_4KB SHIFT_U32(2, 30) 106 #define TCR_RES1 BIT32(31) 107 108 109 /* Normal memory, Inner/Outer Non-cacheable */ 110 #define TCR_XRGNX_NC 0x0 111 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 112 #define TCR_XRGNX_WB 0x1 113 /* Normal memory, Inner/Outer Write-Through Cacheable */ 114 #define TCR_XRGNX_WT 0x2 115 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 116 #define TCR_XRGNX_WBWA 0x3 117 118 /* Non-shareable */ 119 #define TCR_SHX_NSH 0x0 120 /* Outer Shareable */ 121 #define TCR_SHX_OSH 0x2 122 /* Inner Shareable */ 123 #define TCR_SHX_ISH 0x3 124 125 #define ESR_EC_SHIFT 26 126 #define ESR_EC_MASK 0x3f 127 128 #define ESR_EC_UNKNOWN 0x00 129 #define ESR_EC_WFI 0x01 130 #define ESR_EC_AARCH32_CP15_32 0x03 131 #define ESR_EC_AARCH32_CP15_64 0x04 132 #define ESR_EC_AARCH32_CP14_MR 0x05 133 #define ESR_EC_AARCH32_CP14_LS 0x06 134 #define ESR_EC_FP_ASIMD 0x07 135 #define ESR_EC_AARCH32_CP10_ID 0x08 136 #define ESR_EC_AARCH32_CP14_64 0x0c 137 #define ESR_EC_ILLEGAL 0x0e 138 #define ESR_EC_AARCH32_SVC 0x11 139 #define ESR_EC_AARCH64_SVC 0x15 140 #define ESR_EC_AARCH64_SYS 0x18 141 #define ESR_EC_IABT_EL0 0x20 142 #define ESR_EC_IABT_EL1 0x21 143 #define ESR_EC_PC_ALIGN 0x22 144 #define ESR_EC_DABT_EL0 0x24 145 #define ESR_EC_DABT_EL1 0x25 146 #define ESR_EC_SP_ALIGN 0x26 147 #define ESR_EC_AARCH32_FP 0x28 148 #define ESR_EC_AARCH64_FP 0x2c 149 #define ESR_EC_SERROR 0x2f 150 #define ESR_EC_BREAKPT_EL0 0x30 151 #define ESR_EC_BREAKPT_EL1 0x31 152 #define ESR_EC_SOFTSTP_EL0 0x32 153 #define ESR_EC_SOFTSTP_EL1 0x33 154 #define ESR_EC_WATCHPT_EL0 0x34 155 #define ESR_EC_WATCHPT_EL1 0x35 156 #define ESR_EC_AARCH32_BKPT 0x38 157 #define ESR_EC_AARCH64_BRK 0x3c 158 159 /* Combined defines for DFSC and IFSC */ 160 #define ESR_FSC_MASK 0x3f 161 #define ESR_FSC_SIZE_L0 0x00 162 #define ESR_FSC_SIZE_L1 0x01 163 #define ESR_FSC_SIZE_L2 0x02 164 #define ESR_FSC_SIZE_L3 0x03 165 #define ESR_FSC_TRANS_L0 0x04 166 #define ESR_FSC_TRANS_L1 0x05 167 #define ESR_FSC_TRANS_L2 0x06 168 #define ESR_FSC_TRANS_L3 0x07 169 #define ESR_FSC_ACCF_L1 0x09 170 #define ESR_FSC_ACCF_L2 0x0a 171 #define ESR_FSC_ACCF_L3 0x0b 172 #define ESR_FSC_PERMF_L1 0x0d 173 #define ESR_FSC_PERMF_L2 0x0e 174 #define ESR_FSC_PERMF_L3 0x0f 175 #define ESR_FSC_ALIGN 0x21 176 177 /* WnR for DABT and RES0 for IABT */ 178 #define ESR_ABT_WNR BIT32(6) 179 180 #define CPACR_EL1_FPEN_SHIFT 20 181 #define CPACR_EL1_FPEN_MASK 0x3 182 #define CPACR_EL1_FPEN_NONE 0x0 183 #define CPACR_EL1_FPEN_EL1 0x1 184 #define CPACR_EL1_FPEN_EL0EL1 0x3 185 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \ 186 & CPACR_EL1_FPEN_MASK) 187 188 189 #define PAR_F BIT32(0) 190 #define PAR_PA_SHIFT 12 191 #define PAR_PA_MASK (BIT64(36) - 1) 192 193 #define TLBI_MVA_SHIFT 12 194 #define TLBI_ASID_SHIFT 48 195 #define TLBI_ASID_MASK 0xff 196 197 #ifndef ASM 198 static inline void isb(void) 199 { 200 asm volatile ("isb"); 201 } 202 203 static inline void dsb(void) 204 { 205 asm volatile ("dsb sy"); 206 } 207 208 static inline void dsb_ish(void) 209 { 210 asm volatile ("dsb ish"); 211 } 212 213 static inline void dsb_ishst(void) 214 { 215 asm volatile ("dsb ishst"); 216 } 217 218 static inline void write_at_s1e1r(uint64_t va) 219 { 220 asm volatile ("at S1E1R, %0" : : "r" (va)); 221 } 222 223 static __always_inline uint64_t read_pc(void) 224 { 225 uint64_t val; 226 227 asm volatile ("adr %0, ." : "=r" (val)); 228 return val; 229 } 230 231 static __always_inline uint64_t read_fp(void) 232 { 233 uint64_t val; 234 235 asm volatile ("mov %0, x29" : "=r" (val)); 236 return val; 237 } 238 239 static inline uint64_t read_pmu_ccnt(void) 240 { 241 uint64_t val; 242 243 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val)); 244 return val; 245 } 246 247 static inline void tlbi_vaae1is(uint64_t mva) 248 { 249 asm volatile ("tlbi vaae1is, %0" : : "r" (mva)); 250 } 251 252 /* 253 * Templates for register read/write functions based on mrs/msr 254 */ 255 256 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \ 257 static inline type read_##reg(void) \ 258 { \ 259 type val; \ 260 \ 261 asm volatile("mrs %0, " #asmreg : "=r" (val)); \ 262 return val; \ 263 } 264 265 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \ 266 static inline void write_##reg(type val) \ 267 { \ 268 asm volatile("msr " #asmreg ", %0" : : "r" (val)); \ 269 } 270 271 #define DEFINE_U32_REG_READ_FUNC(reg) \ 272 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) 273 274 #define DEFINE_U32_REG_WRITE_FUNC(reg) \ 275 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg) 276 277 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \ 278 DEFINE_U32_REG_READ_FUNC(reg) \ 279 DEFINE_U32_REG_WRITE_FUNC(reg) 280 281 #define DEFINE_U64_REG_READ_FUNC(reg) \ 282 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg) 283 284 #define DEFINE_U64_REG_WRITE_FUNC(reg) \ 285 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg) 286 287 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \ 288 DEFINE_U64_REG_READ_FUNC(reg) \ 289 DEFINE_U64_REG_WRITE_FUNC(reg) 290 291 /* 292 * Define register access functions 293 */ 294 295 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1) 296 DEFINE_U32_REG_READWRITE_FUNCS(daif) 297 DEFINE_U32_REG_READWRITE_FUNCS(fpcr) 298 DEFINE_U32_REG_READWRITE_FUNCS(fpsr) 299 300 DEFINE_U32_REG_READ_FUNC(contextidr_el1) 301 DEFINE_U32_REG_READ_FUNC(sctlr_el1) 302 303 /* ARM Generic timer functions */ 304 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0) 305 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0) 306 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1) 307 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1) 308 309 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1) 310 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1) 311 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1) 312 313 DEFINE_U64_REG_READ_FUNC(esr_el1) 314 DEFINE_U64_REG_READ_FUNC(far_el1) 315 DEFINE_U64_REG_READ_FUNC(mpidr_el1) 316 DEFINE_U64_REG_READ_FUNC(par_el1) 317 318 DEFINE_U64_REG_WRITE_FUNC(mair_el1) 319 320 /* Register read/write functions for GICC registers by using system interface */ 321 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 322 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4) 323 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0) 324 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0) 325 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1) 326 #endif /*ASM*/ 327 328 #endif /*ARM64_H*/ 329 330