1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * 6 * Peng Fan <peng.fan@nxp.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <arm32.h> 31 #include <io.h> 32 #include <kernel/generic_boot.h> 33 #include <kernel/tz_ssvce_def.h> 34 #include <kernel/tz_ssvce_pl310.h> 35 #include <mm/core_memprot.h> 36 #include <mm/core_mmu.h> 37 #include <platform_config.h> 38 #include <stdint.h> 39 40 register_phys_mem(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_DEVICE_SIZE); 41 42 void arm_cl2_config(vaddr_t pl310_base) 43 { 44 /* Disable PL310 */ 45 write32(0, pl310_base + PL310_CTRL); 46 47 write32(PL310_TAG_RAM_CTRL_INIT, pl310_base + PL310_TAG_RAM_CTRL); 48 write32(PL310_DATA_RAM_CTRL_INIT, pl310_base + PL310_DATA_RAM_CTRL); 49 write32(PL310_AUX_CTRL_INIT, pl310_base + PL310_AUX_CTRL); 50 write32(PL310_PREFETCH_CTRL_INIT, pl310_base + PL310_PREFETCH_CTRL); 51 write32(PL310_POWER_CTRL_INIT, pl310_base + PL310_POWER_CTRL); 52 53 /* invalidate all cache ways */ 54 arm_cl2_invbyway(pl310_base); 55 } 56 57 void arm_cl2_enable(vaddr_t pl310_base) 58 { 59 uint32_t val; 60 61 /* Enable PL310 ctrl -> only set lsb bit */ 62 write32(1, pl310_base + PL310_CTRL); 63 64 /* if L2 FLZW enable, enable in L1 */ 65 val = read32(pl310_base + PL310_AUX_CTRL); 66 if (val & 1) 67 write_actlr(read_actlr() | (1 << 3)); 68 } 69 70 vaddr_t pl310_base(void) 71 { 72 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_SEC); 73 } 74 75