1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef PLAT_IMX_IMX_REGS_H 31 #define PLAT_IMX_IMX_REGS_H 32 33 #ifdef CFG_MX6 34 #define UART1_BASE 0x2020000 35 #define IOMUXC_BASE 0x020E0000 36 #define IOMUXC_SIZE 0x4000 37 #define IOMUXC_GPR_BASE 0x020E4000 38 #define SRC_BASE 0x020D8000 39 #define SRC_SIZE 0x4000 40 #define CCM_BASE 0x020C4000 41 #define CCM_SIZE 0x4000 42 #define ANATOP_BASE 0x020C8000 43 #define ANATOP_SIZE 0x1000 44 #define SNVS_BASE 0x020CC000 45 #define GPC_BASE 0x020DC000 46 #define GPC_SIZE 0x4000 47 #define WDOG_BASE 0x020BC000 48 #define SEMA4_BASE 0x02290000 49 #define SEMA4_SIZE 0x4000 50 #define MMDC_P0_BASE 0x021B0000 51 #define MMDC_P0_SIZE 0x4000 52 #define MMDC_P1_BASE 0x021B4000 53 #define MMDC_P1_SIZE 0x4000 54 #define TZASC_BASE 0x21D0000 55 #define TZASC2_BASE 0x21D4000 56 #define UART2_BASE 0x021E8000 57 #define UART3_BASE 0x021EC000 58 #define UART4_BASE 0x021F0000 59 #define UART5_BASE 0x021F4000 60 #define AIPS1_BASE 0x02000000 61 #define AIPS1_SIZE 0x100000 62 #define AIPS2_BASE 0x02100000 63 #define AIPS2_SIZE 0x100000 64 #define AIPS3_BASE 0x02200000 65 #define AIPS3_SIZE 0x100000 66 67 #define SCU_BASE 0x00A00000 68 #define PL310_BASE 0x00A02000 69 #define SRC_BASE 0x020D8000 70 #define IRAM_BASE 0x00900000 71 72 #define OCOTP_BASE 0x021BC000 73 74 #define GIC_BASE 0x00A00000 75 #define GICD_OFFSET 0x1000 76 77 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) 78 #define GICC_OFFSET 0x2000 79 /* No CAAM on i.MX6ULL */ 80 #define CAAM_BASE 0x02140000 81 #else 82 #define GICC_OFFSET 0x100 83 #define CAAM_BASE 0x02100000 84 #endif 85 86 #define GIC_CPU_BASE (GIC_BASE + GICC_OFFSET) 87 #define GIC_DIST_BASE (GIC_BASE + GICD_OFFSET) 88 89 /* Central Security Unit register values */ 90 #define CSU_BASE 0x021C0000 91 #define CSU_CSL_START 0x0 92 #define CSU_CSL_END 0xA0 93 #define CSU_CSL5 0x14 94 #define CSU_CSL15 0x3C 95 #define CSU_CSL16 0x40 96 #define CSU_ACCESS_ALL 0x00FF00FF 97 #define CSU_SETTING_LOCK 0x01000100 98 99 /* Used in suspend/resume and low power idle */ 100 #define MX6Q_SRC_GPR1 0x20 101 #define MX6Q_SRC_GPR2 0x24 102 #define MX6Q_MMDC_MISC 0x18 103 #define MX6Q_MMDC_MAPSR 0x404 104 #define MX6Q_MMDC_MPDGCTRL0 0x83c 105 #define MX6Q_GPC_IMR1 0x08 106 #define MX6Q_GPC_IMR2 0x0c 107 #define MX6Q_GPC_IMR3 0x10 108 #define MX6Q_GPC_IMR4 0x14 109 #define MX6Q_CCM_CCR 0x0 110 #define MX6Q_ANATOP_CORE 0x140 111 112 #define IOMUXC_GPR9_OFFSET 0x24 113 #define IOMUXC_GPR10_OFFSET 0x28 114 115 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET 5 116 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK GENMASK_32(10, 5) 117 118 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET 4 119 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK GENMASK_32(4, 4) 120 121 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET 20 122 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK GENMASK_32(20, 20) 123 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET 21 124 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK GENMASK_32(26, 21) 125 126 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_OFFSET_6UL 11 127 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL GENMASK_32(15, 11) 128 #define IOMUXC_GPR10_OCRAM_TZ_EN_OFFSET_6UL 10 129 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL GENMASK_32(10, 10) 130 131 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_OFFSET_6UL 26 132 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL GENMASK_32(26, 26) 133 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_OFFSET_6UL (27) 134 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27) 135 136 #if defined(CFG_MX6UL) || defined(CFG_MX6ULL) || defined(CFG_MX6SX) 137 #define DRAM0_BASE 0x80000000 138 #else 139 #define DRAM0_BASE 0x10000000 140 #endif 141 142 #elif defined(CFG_MX7) 143 #define GIC_BASE 0x31000000 144 #define GIC_SIZE 0x8000 145 #define GICC_OFFSET 0x2000 146 #define GICD_OFFSET 0x1000 147 148 #define CAAM_BASE 0x30900000 149 #define UART1_BASE 0x30860000 150 #define UART2_BASE 0x30890000 151 #define UART3_BASE 0x30880000 152 153 #define AIPS1_BASE 0x30000000 154 #define AIPS1_SIZE 0x400000 155 #define AIPS2_BASE 0x30400000 156 #define AIPS2_SIZE 0x400000 157 #define AIPS3_BASE 0x30800000 158 #define AIPS3_SIZE 0x400000 159 160 #define WDOG_BASE 0x30280000 161 #define LPSR_BASE 0x30270000 162 #define IOMUXC_BASE 0x30330000 163 #define IOMUXC_GPR_BASE 0x30340000 164 #define OCOTP_BASE 0x30350000 165 #define ANATOP_BASE 0x30360000 166 #define SNVS_BASE 0x30370000 167 #define CCM_BASE 0x30380000 168 #define SRC_BASE 0x30390000 169 #define GPC_BASE 0x303A0000 170 #define TZASC_BASE 0x30780000 171 #define DDRC_PHY_BASE 0x30790000 172 #define MMDC_P0_BASE 0x307A0000 173 #define DDRC_BASE 0x307A0000 174 #define IRAM_BASE 0x00900000 175 #define IRAM_S_BASE 0x00180000 176 177 #define CSU_CSL_START 0x303E0000 178 #define CSU_CSL_END 0x303E0100 179 #define CSU_CSL_59 (0x303E0000 + 59 * 4) 180 #define CSU_CSL_28 (0x303E0000 + 28 * 4) 181 #define CSU_CSL_15 (0x303E0000 + 15 * 4) 182 #define CSU_CSL_12 (0x303E0000 + 12 * 4) 183 #define CSU_ACCESS_ALL 0x00FF00FF 184 #define CSU_SETTING_LOCK 0x01000100 185 186 #define TRUSTZONE_OCRAM_START 0x180000 187 188 #define IOMUXC_GPR9_OFFSET 0x24 189 #define IOMUXC_GPR9_TZASC1_MUX_CONTROL_OFFSET 0 190 191 #define IOMUXC_GPR11_OFFSET 0x2C 192 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_OFFSET 11 193 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11) 194 195 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_OFFSET 10 196 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10) 197 198 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 199 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) 200 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) 201 #else 202 #error "CFG_MX6/7 not defined" 203 #endif 204 205 #define IOMUXC_GPR4_OFFSET 0x10 206 #define IOMUXC_GPR5_OFFSET 0x14 207 #define ARM_WFI_STAT_MASK(n) BIT(n) 208 209 #define ARM_WFI_STAT_MASK_7D(n) BIT(25 + ((n) & 1)) 210 211 #define SRC_SCR 0x000 212 #define SRC_GPR1 0x020 213 #define SRC_GPR2 0x024 214 #define SRC_SCR_CORE1_RST_OFFSET 14 215 #define SRC_SCR_CORE1_ENABLE_OFFSET 22 216 #define SRC_SCR_CPU_ENABLE_ALL SHIFT_U32(0x7, 22) 217 218 #define SRC_GPR1_MX7 0x074 219 #define SRC_A7RCR0 0x004 220 #define SRC_A7RCR1 0x008 221 #define SRC_A7RCR0_A7_CORE_RESET0_OFFSET 0 222 #define SRC_A7RCR1_A7_CORE1_ENABLE_OFFSET 1 223 224 #define WCR_OFF 0 225 226 #define OFFSET_DIGPROG 0x260 227 #define OFFSET_DIGPROG_IMX6SL 0x280 228 #define OFFSET_DIGPROG_IMX7D 0x800 229 230 /* GPC V2 */ 231 #define GPC_PGC_C1 0x840 232 #define GPC_PGC_C1_PUPSCR 0x844 233 234 #define GPC_PGC_PCG_MASK BIT(0) 235 236 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 237 #define GPC_PU_PGC_SW_PUP_REQ 0xf8 238 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc 239 #define GPC_PU_PGC_SW_PDN_REQ 0x104 240 #define GPC_PGC_SW_PDN_PUP_REQ_CORE1_MASK BIT(1) 241 #endif 242