1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 */ 6 #ifndef ARM_H 7 #define ARM_H 8 9 #include <util.h> 10 11 #define MPIDR_CPU_MASK 0xff 12 #define MPIDR_CLUSTER_SHIFT 8 13 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 14 15 16 /* CLIDR definitions */ 17 #define CLIDR_LOUIS_SHIFT 21 18 #define CLIDR_LOC_SHIFT 24 19 #define CLIDR_FIELD_WIDTH 3 20 21 /* CSSELR definitions */ 22 #define CSSELR_LEVEL_SHIFT 1 23 24 /* CTR definitions */ 25 #define CTR_CWG_SHIFT 24 26 #define CTR_CWG_MASK 0xf 27 #define CTR_ERG_SHIFT 20 28 #define CTR_ERG_MASK 0xf 29 #define CTR_DMINLINE_SHIFT 16 30 #define CTR_DMINLINE_WIDTH 4 31 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 32 #define CTR_L1IP_SHIFT 14 33 #define CTR_L1IP_MASK 0x3 34 #define CTR_IMINLINE_SHIFT 0 35 #define CTR_IMINLINE_MASK 0xf 36 37 #define ARM32_CPSR_MODE_MASK 0x1f 38 #define ARM32_CPSR_MODE_USR 0x10 39 #define ARM32_CPSR_MODE_FIQ 0x11 40 #define ARM32_CPSR_MODE_IRQ 0x12 41 #define ARM32_CPSR_MODE_SVC 0x13 42 #define ARM32_CPSR_MODE_MON 0x16 43 #define ARM32_CPSR_MODE_ABT 0x17 44 #define ARM32_CPSR_MODE_UND 0x1b 45 #define ARM32_CPSR_MODE_SYS 0x1f 46 47 #define ARM32_CPSR_T (1 << 5) 48 #define ARM32_CPSR_F_SHIFT 6 49 #define ARM32_CPSR_F (1 << 6) 50 #define ARM32_CPSR_I (1 << 7) 51 #define ARM32_CPSR_A (1 << 8) 52 #define ARM32_CPSR_E (1 << 9) 53 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 54 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 55 #define ARM32_CPSR_IT_MASK1 0x06000000 56 #define ARM32_CPSR_IT_MASK2 0x0000fc00 57 58 /* ARM Generic timer definitions */ 59 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 60 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 61 62 #ifdef ARM32 63 #include <arm32.h> 64 #endif 65 66 #ifdef ARM64 67 #include <arm64.h> 68 #endif 69 70 #endif /*ARM_H*/ 71