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Searched refs:rate (Results 1 – 25 of 287) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1106.c79 u32 con, sel, rate; in rv1106_peri_get_clk() local
86 rate = 400 * MHz; in rv1106_peri_get_clk()
88 rate = 200 * MHz; in rv1106_peri_get_clk()
90 rate = 100 * MHz; in rv1106_peri_get_clk()
92 rate = OSC_HZ; in rv1106_peri_get_clk()
98 rate = 200 * MHz; in rv1106_peri_get_clk()
100 rate = 100 * MHz; in rv1106_peri_get_clk()
102 rate = 50 * MHz; in rv1106_peri_get_clk()
104 rate = OSC_HZ; in rv1106_peri_get_clk()
110 rate = 100 * MHz; in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3562.c63 .rate = _rate##U, \
157 const struct rockchip_cpu_rate_table *rate; in rk3562_armclk_set_rate() local
161 rate = rockchip_get_cpu_settings(rk3562_cpu_rates, new_rate); in rk3562_armclk_set_rate()
162 if (!rate) { in rk3562_armclk_set_rate()
174 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
176 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
183 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
185 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
189 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
191 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
[all …]
H A Dclk_rk3506.c77 .rate = _rate##U, \
128 ulong rate; in soc_clk_dump() local
161 rate = clk_get_rate(&clk); in soc_clk_dump()
164 if (rate < 0) in soc_clk_dump()
169 rate / 1000); in soc_clk_dump()
171 if (rate < 0) in soc_clk_dump()
176 rate / 1000); in soc_clk_dump()
209 const struct rockchip_cpu_rate_table *rate; in rk3506_armclk_set_rate() local
214 rate = rockchip_get_cpu_settings(rk3506_cpu_rates, new_rate); in rk3506_armclk_set_rate()
215 if (!rate) { in rk3506_armclk_set_rate()
[all …]
H A Dclk_rk3568.c25 .rate = _rate##U, \
118 ulong pll_id, ulong rate) in rk3568_pmu_pll_set_rate() argument
134 pmu_priv->pmucru, pll_id, rate); in rk3568_pmu_pll_set_rate()
226 ulong rate) in rk3568_rtc32k_set_pmuclk() argument
234 rational_best_approximation(rate, OSC_HZ, in rk3568_rtc32k_set_pmuclk()
263 ulong clk_id, ulong rate) in rk3568_i2c_set_pmuclk() argument
268 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_i2c_set_pmuclk()
307 ulong clk_id, ulong rate) in rk3568_pwm_set_pmuclk() argument
314 if (rate == OSC_HZ) { in rk3568_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pwm_set_pmuclk()
[all …]
H A Dclk_rv1103b.c65 u32 con, sel, div, rate, prate; in rv1103b_peri_get_clk() local
72 rate = 600 * MHz; in rv1103b_peri_get_clk()
74 rate = 480 * MHz; in rv1103b_peri_get_clk()
76 rate = 400 * MHz; in rv1103b_peri_get_clk()
82 rate = 300 * MHz; in rv1103b_peri_get_clk()
84 rate = 200 * MHz; in rv1103b_peri_get_clk()
89 rate = DIV_TO_RATE(rv1103b_peri_get_clk(priv, LSCLK_PERI_SRC), in rv1103b_peri_get_clk()
93 rate = DIV_TO_RATE(priv->gpll_hz, 11); in rv1103b_peri_get_clk()
104 rate = DIV_TO_RATE(prate, div); in rv1103b_peri_get_clk()
110 return rate; in rv1103b_peri_get_clk()
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H A Dclk_pll.c272 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings() argument
276 while (rate_table->rate) { in rockchip_get_pll_settings()
277 if (rate_table->rate == rate) in rockchip_get_pll_settings()
281 if (rate_table->rate != rate) { in rockchip_get_pll_settings()
283 return rk3588_pll_clk_set_by_auto(24 * MHZ, rate); in rockchip_get_pll_settings()
285 return rockchip_pll_clk_set_by_auto(24 * MHZ, rate); in rockchip_get_pll_settings()
295 const struct rockchip_pll_rate_table *rate; in rk3036_pll_set_rate() local
298 rate = rockchip_get_pll_settings(pll, drate); in rk3036_pll_set_rate()
299 if (!rate) { in rk3036_pll_set_rate()
305 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
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H A Dclk_rk3576.c172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
182 rate = DIV_TO_RATE(priv->cpll_hz , div); in rk3576_bus_get_clk()
184 rate = DIV_TO_RATE(priv->gpll_hz, div); in rk3576_bus_get_clk()
191 rate = 198 * MHz; in rk3576_bus_get_clk()
193 rate = 100 * MHz; in rk3576_bus_get_clk()
195 rate = 50 * MHz; in rk3576_bus_get_clk()
197 rate = OSC_HZ; in rk3576_bus_get_clk()
204 rate = 100 * MHz; in rk3576_bus_get_clk()
206 rate = 50 * MHz; in rk3576_bus_get_clk()
208 rate = OSC_HZ; in rk3576_bus_get_clk()
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H A Dclk_rk3588.c154 u32 con, sel, rate; in rk3588_center_get_clk() local
162 rate = 702 * MHz; in rk3588_center_get_clk()
164 rate = 396 * MHz; in rk3588_center_get_clk()
166 rate = 200 * MHz; in rk3588_center_get_clk()
168 rate = OSC_HZ; in rk3588_center_get_clk()
175 rate = 500 * MHz; in rk3588_center_get_clk()
177 rate = 250 * MHz; in rk3588_center_get_clk()
179 rate = 100 * MHz; in rk3588_center_get_clk()
181 rate = OSC_HZ; in rk3588_center_get_clk()
188 rate = 396 * MHz; in rk3588_center_get_clk()
[all …]
H A Dclk_rk3528.c84 .rate = _rate##U, \
197 const struct rockchip_cpu_rate_table *rate; in rk3528_armclk_set_clk() local
201 rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate); in rk3528_armclk_set_clk()
202 if (!rate) { in rk3528_armclk_set_clk()
217 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); in rk3528_armclk_set_clk()
220 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); in rk3528_armclk_set_clk()
223 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); in rk3528_armclk_set_clk()
226 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); in rk3528_armclk_set_clk()
279 ulong clk_id, ulong rate) in rk3528_ppll_matrix_set_rate() argument
314 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3528_ppll_matrix_set_rate()
[all …]
H A Dclk_rv1126.c25 .rate = _rate##U, \
99 ulong rate);
157 static ulong rv1126_gpll_set_pmuclk(struct rv1126_pmuclk_priv *pmu_priv, ulong rate) in rv1126_gpll_set_pmuclk() argument
172 if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { in rv1126_gpll_set_pmuclk()
173 printf("%s: failed to set gpll rate %lu\n", __func__, rate); in rv1126_gpll_set_pmuclk()
195 ulong rate) in rv1126_rtc32k_set_pmuclk() argument
203 rational_best_approximation(rate, OSC_HZ, in rv1126_rtc32k_set_pmuclk()
236 ulong clk_id, ulong rate) in rv1126_i2c_set_pmuclk() argument
241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
289 ulong clk_id, ulong rate) in rv1126_pwm_set_pmuclk() argument
[all …]
H A Dclk_rv1126b.c78 u32 con, sel, rate; in rv1126b_peri_get_clk() local
85 rate = 200 * MHz; in rv1126b_peri_get_clk()
87 rate = OSC_HZ; in rv1126b_peri_get_clk()
93 rate = 100 * MHz; in rv1126b_peri_get_clk()
95 rate = OSC_HZ; in rv1126b_peri_get_clk()
101 rate = 600 * MHz; in rv1126b_peri_get_clk()
103 rate = 400 * MHz; in rv1126b_peri_get_clk()
105 rate = 200 * MHz; in rv1126b_peri_get_clk()
110 rate = 100 * MHz; in rv1126b_peri_get_clk()
116 rate = 400 * MHz; in rv1126b_peri_get_clk()
[all …]
H A Dclk_rk3328.c76 .rate = _rate##U, \
121 const struct rockchip_cpu_rate_table *rate; in rk3328_armclk_set_clk() local
124 rate = rockchip_get_cpu_settings(rk3328_cpu_rates, hz); in rk3328_armclk_set_clk()
125 if (!rate) { in rk3328_armclk_set_clk()
147 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3328_armclk_set_clk()
148 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3328_armclk_set_clk()
152 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3328_armclk_set_clk()
153 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3328_armclk_set_clk()
243 static ulong rk3328_gmac2io_set_clk(struct rk3328_clk_priv *priv, ulong rate) in rk3328_gmac2io_set_clk() argument
258 ret = rate; in rk3328_gmac2io_set_clk()
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H A Dclk_rk3308.c39 .rate = _rate##U, \
140 const struct rockchip_cpu_rate_table *rate; in rk3308_armclk_set_clk() local
143 rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz); in rk3308_armclk_set_clk()
144 if (!rate) { in rk3308_armclk_set_clk()
163 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3308_armclk_set_clk()
164 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
171 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3308_armclk_set_clk()
172 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
932 ulong rate = 0; in rk3308_clk_get_rate() local
939 rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_clk_get_rate()
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H A Dclk_px30.c35 .rate = _rate##U, \
46 .rate = _rate##U, \
109 struct pll_rate_table *rate = &auto_table; in pll_clk_set_by_auto() local
139 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
160 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
170 return rate; in pll_clk_set_by_auto()
173 static const struct pll_rate_table *get_pll_settings(unsigned long rate) in get_pll_settings() argument
179 if (rate == px30_pll_rates[i].rate) in get_pll_settings()
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H A Dclk_rk3368.c32 ulong rate; member
41 .rate = _rate##U, \
92 .rate = _rate##U, \
135 if (freq_hz == rk3368_pll_rates[i].rate) in rkclk_get_pll_config()
295 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
328 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
330 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate); in rk3368_mmc_get_clk()
331 return rate >> 1; in rk3368_mmc_get_clk()
335 ulong rate, in rk3368_mmc_find_best_rate_and_parent() argument
344 ulong rate; in rk3368_mmc_find_best_rate_and_parent() member
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H A Dclk_rk3128.c52 .rate = _rate##U, \
94 const struct rockchip_cpu_rate_table *rate; in rk3128_armclk_set_clk() local
97 rate = rockchip_get_cpu_settings(rk3128_cpu_rates, hz); in rk3128_armclk_set_clk()
98 if (!rate) { in rk3128_armclk_set_clk()
120 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3128_armclk_set_clk()
121 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3128_armclk_set_clk()
125 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3128_armclk_set_clk()
126 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3128_armclk_set_clk()
532 ulong rate = 0; in rk3128_clk_get_rate() local
539 rate = rockchip_pll_get_rate(&rk3128_pll_clks[clk->id - 1], in rk3128_clk_get_rate()
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-pic32/
H A Dcpu.c26 static ulong rate(int id) in rate() function
31 ulong rate; in rate() local
44 rate = clk_get_rate(&clk); in rate()
48 return rate; in rate()
53 return rate(PB7CLK); in clk_get_cpu_rate()
62 ulong rate; in prefetch_init() local
65 rate = clk_get_cpu_rate() / 1000000; in prefetch_init()
72 if (rate < 66) in prefetch_init()
74 else if (rate < 133) in prefetch_init()
79 if (rate <= 83) in prefetch_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c57 u32 reg, val, rate; in scg_sircdiv_get_rate() local
87 rate = scg_src_get_rate(SCG_SIRC_CLK); in scg_sircdiv_get_rate()
88 rate = rate / (1 << (val - 1)); in scg_sircdiv_get_rate()
90 return rate; in scg_sircdiv_get_rate()
95 u32 reg, val, rate; in scg_fircdiv_get_rate() local
125 rate = scg_src_get_rate(SCG_FIRC_CLK); in scg_fircdiv_get_rate()
126 rate = rate / (1 << (val - 1)); in scg_fircdiv_get_rate()
128 return rate; in scg_fircdiv_get_rate()
133 u32 reg, val, rate; in scg_soscdiv_get_rate() local
163 rate = scg_src_get_rate(SCG_SOSC_CLK); in scg_soscdiv_get_rate()
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c128 unsigned long rate) in rk628_cru_clk_set_rate_pll() argument
130 unsigned long fin = REFCLK_RATE, fout = rate; in rk628_cru_clk_set_rate_pll()
275 unsigned long rate) in rk628_cru_clk_set_rate_sclk_vop() argument
288 rational_best_approximation(rate, parent_rate, in rk628_cru_clk_set_rate_sclk_vop()
293 return rate; in rk628_cru_clk_set_rate_sclk_vop()
298 unsigned long rate, parent_rate, m, n; in rk628_cru_clk_get_rate_sclk_vop() local
312 rate = parent_rate * m / n; in rk628_cru_clk_get_rate_sclk_vop()
314 return rate; in rk628_cru_clk_get_rate_sclk_vop()
319 unsigned long rate, parent_rate, n; in rk628_cru_clk_get_rate_clk_imodet() local
332 rate = parent_rate / (n + 1); in rk628_cru_clk_get_rate_clk_imodet()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-zynq/
H A Dclk.c38 ulong rate; in set_cpu_clk_info() local
52 rate = clk_get_rate(&clk) / 1000000; in set_cpu_clk_info()
54 gd->bd->bi_ddr_freq = rate; in set_cpu_clk_info()
56 gd->bd->bi_arm_freq = rate; in set_cpu_clk_info()
86 unsigned long rate; in soc_clk_dump() local
93 rate = clk_get_rate(&clk); in soc_clk_dump()
97 if (rate == (unsigned long)-ENOSYS) in soc_clk_dump()
100 printf("%10s%20lu\n", name, rate); in soc_clk_dump()
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_pic32.c171 int parent_rate, int rate, int parent_id) in pic32_set_refclk() argument
182 if (parent_rate <= rate) { in pic32_set_refclk()
186 div = parent_rate / (rate << 1); in pic32_set_refclk()
189 do_div(frac, rate); in pic32_set_refclk()
285 u64 rate; in pic32_get_mpll_rate() local
293 rate = (SYS_POSC_CLK_HZ / idiv) * mul; in pic32_get_mpll_rate()
294 do_div(rate, odiv1); in pic32_get_mpll_rate()
295 do_div(rate, odiv2); in pic32_get_mpll_rate()
297 return (ulong)rate; in pic32_get_mpll_rate()
322 ulong rate, pll_hz; in pic32_clk_init() local
[all …]
H A Dclk_sandbox.c14 ulong rate[SANDBOX_CLK_ID_COUNT]; member
25 return priv->rate[clk->id]; in sandbox_clk_get_rate()
28 static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate) in sandbox_clk_set_rate() argument
36 if (!rate) in sandbox_clk_set_rate()
39 old_rate = priv->rate[clk->id]; in sandbox_clk_set_rate()
40 priv->rate[clk->id] = rate; in sandbox_clk_set_rate()
96 return priv->rate[id]; in sandbox_clk_query_rate()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c97 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
98 c->parent->rate); in peri_clk_enable()
161 static int peri_clk_set_rate(struct clk *c, unsigned long rate) in peri_clk_set_rate() argument
172 diff = rate; in peri_clk_set_rate()
183 div = ref->clk.rate / rate; in peri_clk_set_rate()
187 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
190 if (abs(new_rate - rate) < diff) { in peri_clk_set_rate()
191 diff = abs(new_rate - rate); in peri_clk_set_rate()
194 c->rate = new_rate; in peri_clk_set_rate()
200 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c97 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
98 c->parent->rate); in peri_clk_enable()
161 static int peri_clk_set_rate(struct clk *c, unsigned long rate) in peri_clk_set_rate() argument
172 diff = rate; in peri_clk_set_rate()
183 div = ref->clk.rate / rate; in peri_clk_set_rate()
187 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
190 if (abs(new_rate - rate) < diff) { in peri_clk_set_rate()
191 diff = abs(new_rate - rate); in peri_clk_set_rate()
194 c->rate = new_rate; in peri_clk_set_rate()
200 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
[all …]
/rk3399_rockchip-uboot/drivers/clk/aspeed/
H A Dclk_ast2500.c120 ulong rate; in ast2500_clk_get_rate() local
129 rate = ast2500_get_hpll_rate(clkin, in ast2500_clk_get_rate()
133 rate = ast2500_get_mpll_rate(clkin, in ast2500_clk_get_rate()
141 rate = ast2500_get_hpll_rate(clkin, in ast2500_clk_get_rate()
144 rate = rate / apb_div; in ast2500_clk_get_rate()
148 rate = ast2500_get_uart_clk_rate(priv->scu, 1); in ast2500_clk_get_rate()
151 rate = ast2500_get_uart_clk_rate(priv->scu, 2); in ast2500_clk_get_rate()
154 rate = ast2500_get_uart_clk_rate(priv->scu, 3); in ast2500_clk_get_rate()
157 rate = ast2500_get_uart_clk_rate(priv->scu, 4); in ast2500_clk_get_rate()
160 rate = ast2500_get_uart_clk_rate(priv->scu, 5); in ast2500_clk_get_rate()
[all …]

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