clk: rk3328: Implement the gmac2phy clock assignment

Implement the setting parent and rate for gmac2phy clock, and
add internal pll div set for gmac2phy clk.

Change-Id: I6d083a562979c3f9ef71fa581d9

clk: rk3328: Implement the gmac2phy clock assignment

Implement the setting parent and rate for gmac2phy clock, and
add internal pll div set for gmac2phy clk.

Change-Id: I6d083a562979c3f9ef71fa581d90af1b3ecb9aa9
Signed-off-by: David Wu <david.wu@rock-chips.com>

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clk: rockchip: rk3328: fix up the bus and peri aclk div overflow

Change-Id: I3983af87bec9bd79280914c803f0af3d5e3ffbb0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

Merge branch 'next-dev' into thunder-boot

rockchip: drivers: clk: rk3328: add spi clk config for spl and uboot

Change-Id: I12da02d52e3c4aec64fbd6a378cd40e96c3775ce
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>

clk: rockchip: rk3328: add case SCLK_EMMC_SAMPLE

Change-Id: Id2769eefc1692422110152e6dbec7afeb4488c8c
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>

clk: rockchip: rk3328: print arm enter and init rate

Change-Id: I80ebeee0d6d8b151061d0bbb0d1d12070dcc6f98
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3328: support crypto clk setting

Change-Id: I9e4d58050b087c3da6649efe4d3115da2ce6dce7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3328: add clk_set_defaults for cru node

Change-Id: I715dde89f691fd95487db53569cc6d8164dc5f28
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: mmc: add mmc set and get phase

add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chi

clk: rockchip: mmc: add mmc set and get phase

add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: support clk_tsadc setting freq

Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3328: replenish some CLK settings

Change-Id: I33e6ff57c2d616c933a458dade9a751460d0bc9a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3328: support more clks to set and get rate

Change-Id: Ic231b7701c6eb23b0e9db21c1d28fb4d08c4debf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3328: convert to live dt

Use dev_read_addr_ptr to get cru base

Change-Id: I6bae4b3e540f2d70f50615bf7cff0af99908f859
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

clk: rockchip: Add rk3328 gamc clock support

The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.

Change-Id: I4963f

clk: rockchip: Add rk3328 gamc clock support

The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.

Change-Id: I4963f03f6aea2c7196f33dae0bca38a432c80690
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: clk: don't reture error when not found reset driver

It's OK to continue work without reset driver.

Change-Id: I7addc19cd0a6fbbc3ebd07c1686067e5e8f4225f
Signed-off-by: Kever Yang <kever.ya

rockchip: clk: don't reture error when not found reset driver

It's OK to continue work without reset driver.

Change-Id: I7addc19cd0a6fbbc3ebd07c1686067e5e8f4225f
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.co

rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clk: Add rk3328 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Change-Id: I73

rockchip: clk: Add rk3328 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Change-Id: I73608db35c926470692eb982e881b01e52fcf2d9
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit b375d84135e26d5ec5034a515af4df5981785f37)

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC w

rockchip: clk: update dwmmc clock div

dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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dm: Rename dev_addr..() functions

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing function

dm: Rename dev_addr..() functions

These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

1. dev_read_addr...() - works on devices, supports flat/live tree
2. devfdt_get_addr...() - current functions, flat tree only
3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-rockchip

This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.

rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <s

rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC

The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it bo

Merge git://git.denx.de/u-boot-rockchip

This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang. Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).

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rockchip: rk3328: add clock driver

Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips

rockchip: rk3328: add clock driver

Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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