Lines Matching refs:rate

39 	.rate	= _rate##U,					\
140 const struct rockchip_cpu_rate_table *rate; in rk3308_armclk_set_clk() local
143 rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz); in rk3308_armclk_set_clk()
144 if (!rate) { in rk3308_armclk_set_clk()
163 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3308_armclk_set_clk()
164 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
171 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3308_armclk_set_clk()
172 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rk3308_armclk_set_clk()
932 ulong rate = 0; in rk3308_clk_get_rate() local
939 rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_clk_get_rate()
943 rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_clk_get_rate()
947 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_clk_get_rate()
951 rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_clk_get_rate()
959 rate = rk3308_mmc_get_clk(clk); in rk3308_clk_get_rate()
965 rate = rk3308_i2c_get_clk(clk); in rk3308_clk_get_rate()
968 rate = rk3308_saradc_get_clk(clk); in rk3308_clk_get_rate()
971 rate = rk3308_tsadc_get_clk(clk); in rk3308_clk_get_rate()
975 rate = rk3308_spi_get_clk(clk); in rk3308_clk_get_rate()
980 rate = rk3308_pwm_get_clk(clk); in rk3308_clk_get_rate()
983 rate = rk3308_vop_get_clk(clk); in rk3308_clk_get_rate()
989 rate = rk3308_bus_get_clk(priv, clk->id); in rk3308_clk_get_rate()
994 rate = rk3308_peri_get_clk(priv, clk->id); in rk3308_clk_get_rate()
998 rate = rk3308_audio_get_clk(priv, clk->id); in rk3308_clk_get_rate()
1002 rate = rk3308_crypto_get_clk(priv, clk->id); in rk3308_clk_get_rate()
1005 rate = rk3308_rtc32k_get_clk(priv, clk->id); in rk3308_clk_get_rate()
1008 rate = rk3308_sclk_sfc_get_clk(priv); in rk3308_clk_get_rate()
1014 return rate; in rk3308_clk_get_rate()
1017 static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) in rk3308_clk_set_rate() argument
1022 debug("%s %ld %ld\n", __func__, clk->id, rate); in rk3308_clk_set_rate()
1027 DPLL, rate); in rk3308_clk_set_rate()
1040 (rate < rockchip_pll_get_rate(&rk3308_pll_clks[APLL], in rk3308_clk_set_rate()
1042 rk3308_armclk_set_clk(priv, rate); in rk3308_clk_set_rate()
1043 priv->armclk_hz = rate; in rk3308_clk_set_rate()
1049 ret = rk3308_mmc_set_clk(clk, rate); in rk3308_clk_set_rate()
1055 ret = rk3308_i2c_set_clk(clk, rate); in rk3308_clk_set_rate()
1058 ret = rk3308_mac_set_clk(clk, rate); in rk3308_clk_set_rate()
1061 ret = rk3308_mac_set_speed_clk(clk, rate); in rk3308_clk_set_rate()
1064 ret = rk3308_saradc_set_clk(clk, rate); in rk3308_clk_set_rate()
1067 ret = rk3308_tsadc_set_clk(clk, rate); in rk3308_clk_set_rate()
1071 ret = rk3308_spi_set_clk(clk, rate); in rk3308_clk_set_rate()
1076 ret = rk3308_pwm_set_clk(clk, rate); in rk3308_clk_set_rate()
1079 ret = rk3308_vop_set_clk(clk, rate); in rk3308_clk_set_rate()
1084 rate = rk3308_bus_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1089 rate = rk3308_peri_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1093 rate = rk3308_audio_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1097 ret = rk3308_crypto_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1100 ret = rk3308_rtc32k_set_clk(priv, clk->id, rate); in rk3308_clk_set_rate()
1103 ret = rk3308_sclk_sfc_set_clk(priv, rate); in rk3308_clk_set_rate()
1131 ulong rate; in rockchip_mmc_get_phase() local
1133 rate = rk3308_clk_get_rate(clk); in rockchip_mmc_get_phase()
1135 if (rate < 0) in rockchip_mmc_get_phase()
1136 return rate; in rockchip_mmc_get_phase()
1149 36 * (rate / 1000000); in rockchip_mmc_get_phase()
1166 ulong rate; in rockchip_mmc_set_phase() local
1168 rate = rk3308_clk_get_rate(clk); in rockchip_mmc_set_phase()
1170 if (rate < 0) in rockchip_mmc_set_phase()
1171 return rate; in rockchip_mmc_set_phase()
1182 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rockchip_mmc_set_phase()
1403 unsigned long rate; in soc_clk_dump() local
1429 rate = clk_get_rate(&clk); in soc_clk_dump()
1432 if (rate < 0) in soc_clk_dump()
1437 rate / 1000); in soc_clk_dump()
1439 if (rate < 0) in soc_clk_dump()
1444 rate / 1000); in soc_clk_dump()