Lines Matching refs:rate
154 u32 con, sel, rate; in rk3588_center_get_clk() local
162 rate = 702 * MHz; in rk3588_center_get_clk()
164 rate = 396 * MHz; in rk3588_center_get_clk()
166 rate = 200 * MHz; in rk3588_center_get_clk()
168 rate = OSC_HZ; in rk3588_center_get_clk()
175 rate = 500 * MHz; in rk3588_center_get_clk()
177 rate = 250 * MHz; in rk3588_center_get_clk()
179 rate = 100 * MHz; in rk3588_center_get_clk()
181 rate = OSC_HZ; in rk3588_center_get_clk()
188 rate = 396 * MHz; in rk3588_center_get_clk()
190 rate = 200 * MHz; in rk3588_center_get_clk()
192 rate = 100 * MHz; in rk3588_center_get_clk()
194 rate = OSC_HZ; in rk3588_center_get_clk()
201 rate = 200 * MHz; in rk3588_center_get_clk()
203 rate = 100 * MHz; in rk3588_center_get_clk()
205 rate = 50 * MHz; in rk3588_center_get_clk()
207 rate = OSC_HZ; in rk3588_center_get_clk()
213 return rate; in rk3588_center_get_clk()
217 ulong clk_id, ulong rate) in rk3588_center_set_clk() argument
224 if (rate >= 700 * MHz) in rk3588_center_set_clk()
226 else if (rate >= 396 * MHz) in rk3588_center_set_clk()
228 else if (rate >= 200 * MHz) in rk3588_center_set_clk()
237 if (rate >= 500 * MHz) in rk3588_center_set_clk()
239 else if (rate >= 250 * MHz) in rk3588_center_set_clk()
241 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
250 if (rate >= 396 * MHz) in rk3588_center_set_clk()
252 else if (rate >= 198 * MHz) in rk3588_center_set_clk()
254 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
263 if (rate >= 198 * MHz) in rk3588_center_set_clk()
265 else if (rate >= 99 * MHz) in rk3588_center_set_clk()
267 else if (rate >= 50 * MHz) in rk3588_center_set_clk()
286 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
315 rate = 100 * MHz; in rk3588_top_get_clk()
317 rate = 50 * MHz; in rk3588_top_get_clk()
319 rate = OSC_HZ; in rk3588_top_get_clk()
325 return rate; in rk3588_top_get_clk()
329 ulong clk_id, ulong rate) in rk3588_top_set_clk() argument
336 if (!(priv->cpll_hz % rate)) { in rk3588_top_set_clk()
338 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
352 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
362 if (rate == 100 * MHz) in rk3588_top_set_clk()
364 else if (rate == 50 * MHz) in rk3588_top_set_clk()
384 ulong rate; in rk3588_i2c_get_clk() local
427 rate = 200 * MHz; in rk3588_i2c_get_clk()
429 rate = 100 * MHz; in rk3588_i2c_get_clk()
431 return rate; in rk3588_i2c_get_clk()
435 ulong rate) in rk3588_i2c_set_clk() argument
440 if (rate >= 198 * MHz) in rk3588_i2c_set_clk()
529 ulong clk_id, ulong rate) in rk3588_spi_set_clk() argument
534 if (rate >= 198 * MHz) in rk3588_spi_set_clk()
536 else if (rate >= 140 * MHz) in rk3588_spi_set_clk()
613 ulong clk_id, ulong rate) in rk3588_pwm_set_clk() argument
618 if (rate >= 99 * MHz) in rk3588_pwm_set_clk()
620 else if (rate >= 50 * MHz) in rk3588_pwm_set_clk()
686 ulong clk_id, ulong rate) in rk3588_adc_set_clk() argument
693 if (!(OSC_HZ % rate)) { in rk3588_adc_set_clk()
694 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
704 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
716 if (!(OSC_HZ % rate)) { in rk3588_adc_set_clk()
717 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
727 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
812 ulong clk_id, ulong rate) in rk3588_mmc_set_clk() argument
821 if (!(OSC_HZ % rate)) { in rk3588_mmc_set_clk()
823 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_mmc_set_clk()
824 } else if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
826 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
829 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
833 if (!(priv->cpll_hz % rate)) { in rk3588_mmc_set_clk()
835 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
838 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
842 if (!(702 * MHz % rate)) { in rk3588_mmc_set_clk()
844 div = DIV_ROUND_UP(702 * MHz, rate); in rk3588_mmc_set_clk()
847 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
919 ulong clk_id, ulong rate) in rk3588_aux16m_set_clk() argument
929 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aux16m_set_clk()
998 ulong clk_id, ulong rate) in rk3588_aclk_vop_set_clk() argument
1006 if (rate >= 850 * MHz) { in rk3588_aclk_vop_set_clk()
1009 } else if (rate >= 750 * MHz) { in rk3588_aclk_vop_set_clk()
1012 } else if (rate >= 700 * MHz) { in rk3588_aclk_vop_set_clk()
1015 } else if (!(priv->cpll_hz % rate)) { in rk3588_aclk_vop_set_clk()
1017 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_aclk_vop_set_clk()
1020 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_aclk_vop_set_clk()
1029 if (rate == 400 * MHz || rate == 396 * MHz) in rk3588_aclk_vop_set_clk()
1031 else if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1033 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1042 if (rate == 200 * MHz) in rk3588_aclk_vop_set_clk()
1044 else if (rate == 100 * MHz) in rk3588_aclk_vop_set_clk()
1046 else if (rate == 50 * MHz) in rk3588_aclk_vop_set_clk()
1110 ulong clk_id, ulong rate) in rk3588_dclk_vop_set_clk() argument
1160 if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { in rk3588_dclk_vop_set_clk()
1161 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1167 div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); in rk3588_dclk_vop_set_clk()
1175 priv->cru, V0PLL, div * rate); in rk3588_dclk_vop_set_clk()
1197 div = DIV_ROUND_UP(pll_rate, rate); in rk3588_dclk_vop_set_clk()
1201 if (abs(rate - now) < abs(rate - best_rate)) { in rk3588_dclk_vop_set_clk()
1216 printf("do not support this vop freq %lu\n", rate); in rk3588_dclk_vop_set_clk()
1282 ulong clk_id, ulong rate) in rk3588_gmac_set_clk() argument
1287 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_gmac_set_clk()
1384 ulong clk_id, ulong rate) in rk3588_uart_set_rate() argument
1390 if (priv->gpll_hz % rate == 0) { in rk3588_uart_set_rate()
1393 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1394 } else if (priv->cpll_hz % rate == 0) { in rk3588_uart_set_rate()
1397 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_uart_set_rate()
1398 } else if (rate == OSC_HZ) { in rk3588_uart_set_rate()
1406 rational_best_approximation(rate, priv->gpll_hz / div, in rk3588_uart_set_rate()
1494 ulong clk_id, ulong rate) in rk3588_pciephy_set_rate() argument
1499 if (rate == OSC_HZ) { in rk3588_pciephy_set_rate()
1504 div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3588_pciephy_set_rate()
1542 ulong rate = 0; in rk3588_clk_get_rate() local
1556 rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru, in rk3588_clk_get_rate()
1560 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru, in rk3588_clk_get_rate()
1564 rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru, in rk3588_clk_get_rate()
1568 rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_get_rate()
1572 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1576 rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru, in rk3588_clk_get_rate()
1580 rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_get_rate()
1584 rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru, in rk3588_clk_get_rate()
1588 rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru, in rk3588_clk_get_rate()
1595 rate = rk3588_center_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1600 rate = rk3588_top_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1611 rate = rk3588_i2c_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1618 rate = rk3588_spi_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1624 rate = rk3588_pwm_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1628 rate = rk3588_adc_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1635 rate = rk3588_mmc_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1638 rate = OSC_HZ; in rk3588_clk_get_rate()
1649 rate = rk3588_aclk_vop_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1658 rate = rk3588_dclk_vop_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1662 rate = rk3588_clk_csihost_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1668 rate = rk3588_gmac_get_clk(priv, clk->id); in rk3588_clk_get_rate()
1679 rate = rk3588_uart_get_rate(priv, clk->id); in rk3588_clk_get_rate()
1684 rate = rk3588_pciephy_get_rate(priv, clk->id); in rk3588_clk_get_rate()
1691 return rate; in rk3588_clk_get_rate()
1694 static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) in rk3588_clk_set_rate() argument
1712 CPLL, rate); in rk3588_clk_set_rate()
1718 GPLL, rate); in rk3588_clk_set_rate()
1724 NPLL, rate); in rk3588_clk_set_rate()
1728 V0PLL, rate); in rk3588_clk_set_rate()
1734 AUPLL, rate); in rk3588_clk_set_rate()
1740 PPLL, rate); in rk3588_clk_set_rate()
1748 ret = rk3588_center_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1753 ret = rk3588_top_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1764 ret = rk3588_i2c_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1771 ret = rk3588_spi_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1777 ret = rk3588_pwm_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1781 ret = rk3588_adc_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1788 ret = rk3588_mmc_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1796 rk3588_aux16m_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1802 ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1811 ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1817 ret = rk3588_gmac_set_clk(priv, clk->id, rate); in rk3588_clk_set_rate()
1828 ret = rk3588_uart_set_rate(priv, clk->id, rate); in rk3588_clk_set_rate()
1833 ret = rk3588_pciephy_set_rate(priv, clk->id, rate); in rk3588_clk_set_rate()
1861 ulong rate; in rk3588_mmc_get_phase() local
1863 rate = rk3588_clk_get_rate(clk); in rk3588_mmc_get_phase()
1864 if (rate <= 0) in rk3588_mmc_get_phase()
1865 return rate; in rk3588_mmc_get_phase()
1878 36 * (rate / 1000000); in rk3588_mmc_get_phase()
1894 ulong rate; in rk3588_mmc_set_phase() local
1896 rate = rk3588_clk_get_rate(clk); in rk3588_mmc_set_phase()
1897 if (rate <= 0) in rk3588_mmc_set_phase()
1898 return rate; in rk3588_mmc_set_phase()
1909 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3588_mmc_set_phase()
2354 static ulong rk3588_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3588_clk_scmi_set_rate() argument
2369 if (rate >= 700 * MHz) in rk3588_clk_scmi_set_rate()
2381 if ((OSC_HZ % rate) == 0) { in rk3588_clk_scmi_set_rate()
2382 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_clk_scmi_set_rate()
2386 } else if ((SPLL_RATE % rate) == 0) { in rk3588_clk_scmi_set_rate()
2387 div = DIV_ROUND_UP(SPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2392 div = DIV_ROUND_UP(GPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2399 if ((SPLL_RATE % rate) == 0) { in rk3588_clk_scmi_set_rate()
2400 div = DIV_ROUND_UP(SPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2405 div = DIV_ROUND_UP(GPLL_RATE, rate); in rk3588_clk_scmi_set_rate()
2412 if (rate >= 175 * MHz) in rk3588_clk_scmi_set_rate()
2414 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2416 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2425 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2427 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2429 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2438 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2440 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2442 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2451 if (rate >= 350 * MHz) in rk3588_clk_scmi_set_rate()
2453 else if (rate >= 233 * MHz) in rk3588_clk_scmi_set_rate()
2455 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2464 if (rate >= 175 * MHz) in rk3588_clk_scmi_set_rate()
2466 else if (rate >= 116 * MHz) in rk3588_clk_scmi_set_rate()
2468 else if (rate >= 58 * MHz) in rk3588_clk_scmi_set_rate()
2480 if (rate >= 150 * MHz) in rk3588_clk_scmi_set_rate()
2482 else if (rate >= 100 * MHz) in rk3588_clk_scmi_set_rate()
2484 else if (rate >= 50 * MHz) in rk3588_clk_scmi_set_rate()
2524 unsigned long rate; in soc_clk_dump() local
2552 rate = clk_get_rate(&clk); in soc_clk_dump()
2554 if (rate < 0) in soc_clk_dump()
2559 rate / 1000); in soc_clk_dump()