clk: rockchip: rk3308: Don't limit to decrease arm freq

rockchip_wtemp_dvfs.c may decrease the arm freq.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I49fbf8fc11bc3c3cb954ce0393cb7

clk: rockchip: rk3308: Don't limit to decrease arm freq

rockchip_wtemp_dvfs.c may decrease the arm freq.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I49fbf8fc11bc3c3cb954ce0393cb72103cf22b51

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clk: rockchip: rk3308: support more pwm clks

Change-Id: I4ad368e6014eda14cb8ec850a45467e5db6ea947
Signed-off-by: ZhiZhan Chen <zhizhan.chen@rock-chips.com>

clk: rockchip: rk3308: fix up the sclk_rtc32k setting error

Change-Id: I67bb28823c0f031c2523c4174763c567aa43f43c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3308: add support to set and get sfc clock

Change-Id: I322471da6e50b0bad328dde015d0d7d0466cc3a9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Merge branch 'next-dev' into thunder-boot

clk: rockchip: rk3308: Add support to set and get clk_rtc32k clock

Change-Id: Iea481af0c99a2b2ca9d6eff050e96e80845c8478
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Merge branch 'next-dev' into thunder-boot

clk: rockchip: rk3308: drop CONFIG_SPL_BUILD control rules

Change-Id: Iba8a3cfcf201e10630211b1190bf9e95b04cf475
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>

clk: rockchip: rk3308: support pclk_wdt get rate

Change-Id: I001cfef774c9657b6286467dc4ef841771841895
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: Add mac clock support for rk3308

Change-Id: I972e2b7977f0f94164c72ae2205ec51780eb7373
Signed-off-by: David Wu <david.wu@rock-chips.com>

clk: rockchip: rk3308: print arm enter and init rate

Change-Id: I6df66d7b5dda643dba49ee87c2a2c0544ddbcded
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3308: support crypto clk setting

Change-Id: I58967fe70fbae6630fe0404414daaee6b1498b72
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3308: Add flag for clk_set_defaults

Change-Id: Ic9009b35e395cfe8c2a8f8d367b75b85294c7354
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3308: add arm clk 408M support

Change-Id: I133576889860c7bae3f722dcd53df6a50c500c35
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

clk: rockchip: support clk_tsadc setting freq

Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3308: Add clk_set_defaults()

As clk_set_defaults() is removed in device core, so add it in clock
driver.

Change-Id: If09a9ddca27a3d1fc0747d8cafbeaacd8ef97d36
Signed-off-by: Finley

rockchip: clk: rk3308: Add clk_set_defaults()

As clk_set_defaults() is removed in device core, so add it in clock
driver.

Change-Id: If09a9ddca27a3d1fc0747d8cafbeaacd8ef97d36
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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rockchip: clk: rk3308: Add support to set and get armclk rate

Change-Id: I2f4bbed7d6c43f340892968ce8e2ed417f975e97
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: rk3308: Use common apis for setting and getting pll rate

Change-Id: Id60ebe239148c7fa7bb8ca1abb411570596c6e28
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3308: Modify the print format of clk

Change-Id: Idb56e8c662fafe443e8f271046d8b6298b1ca5ec
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: rk3308: Correct clock divisor range assertions

Change-Id: I97e8b1b5c454d9cea4126a302491a63f1d57b430
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3308: check pll rate before set and get rate

As clk_set_defaults() is called before rk3308_clk_probe() and pll rate are
assigned when clk probe at present, so if enable kernel dtb a

clk: rockchip: rk3308: check pll rate before set and get rate

As clk_set_defaults() is called before rk3308_clk_probe() and pll rate are
assigned when clk probe at present, so if enable kernel dtb and it contains
"assigned-clocks" property, the pll rate will be zero when set and get clk rate.
In order to fix this, check and assign pll rate before set and get rate.

Change-Id: Ic8e9fcf487e7531a8ef23f54d0786e0cbc9a9f4a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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clk: rockchip: rk3308: update dpll_hz if dpll rate is changed

Change-Id: I133c4c19968de249902db005fea31648bb69a7fc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3308: Fix divisor for i2c, saradc, pwm and spi

Some divisor calculations were misrounded, causing higher than
requested rates on some clocks. Fix them up using DIV_ROUND_UP.

Change

clk: rockchip: rk3308: Fix divisor for i2c, saradc, pwm and spi

Some divisor calculations were misrounded, causing higher than
requested rates on some clocks. Fix them up using DIV_ROUND_UP.

Change-Id: Ie90598d94e9a8dcde9c68ec9986ea200293c2d5b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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clk: rockchip: Fix clk name of PLL_DPLL

Change-Id: Id2d9e91917a8011d150f499bfc91eae02e5a0642
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3308: implement soc_clk_dump

Change-Id: I6f0c3f56a878f491c4bb1deafd8e020e052e2287
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>