| #
5c6e0812 |
| 17-Jun-2025 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: fix cci\big\litcore init
If core select pvtpll in ddr,not need init in spl.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I653ad0836eb6c05591c2105705c2ee3
clk: rockchip: rk3576: fix cci\big\litcore init
If core select pvtpll in ddr,not need init in spl.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I653ad0836eb6c05591c2105705c2ee3038feeefb
show more ...
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| #
d2c37103 |
| 31-Mar-2025 |
Damon Ding <damon.ding@rock-chips.com> |
clk: rockchip: rk3576: expand pll rate table to support 152.6M vop dclk rate
Change-Id: I7878a38e83c3da436b0dd4f4485c71609e51980a
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
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| #
26b67b4b |
| 31-Mar-2025 |
Damon Ding <damon.ding@rock-chips.com> |
clk: rockchip: rk3576: set RK3576_VOP_PLL_LIMIT_FREQ to 594M
Sync the pll frequency limit with Kernel in order to avoid the
inconsistency of frequency division between Uboot and Kernel when
the pare
clk: rockchip: rk3576: set RK3576_VOP_PLL_LIMIT_FREQ to 594M
Sync the pll frequency limit with Kernel in order to avoid the
inconsistency of frequency division between Uboot and Kernel when
the parent of vop dclk is VPLL.
Change-Id: I667c3ebce04fb772bce8c17b88ff7203b308b755
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
show more ...
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| #
cdb92760 |
| 25-Jul-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add ref_clkout_pll
Change-Id: Id120fafec101568fab94929934667e7bef8c1a09
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
f215d626 |
| 14-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: fix ebc clk setting rule
Change-Id: I33b63df8d595531df85fdac83f20c7ba104c5008
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
4a69562c |
| 28-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add hclk sdmmc/emmc/sdio
Change-Id: I72a7a8ae2b4d0e2e8480f7b2738042069f8b40ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
431b7b81 |
| 19-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add decom clk setting
Change-Id: I3e0e288938d672b86d80dc91e1b782691695c5fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
9e41c644 |
| 26-Mar-2024 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3576: add 1150M for pll table
Change-Id: I4ac24f9c6da58d35c84a88cc2d0273253a55ae9e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
d38d4a65 |
| 07-Mar-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3576: Change cpu rm from 4 to 3 for performance
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3e6d153a35e2615b612d08525c09d117979d9cd1
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| #
7f4710ef |
| 01-Mar-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3576: Enable scmi clk for cpu
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I3ae44067343b44f5c87a36f418bfd670885de1d1
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| #
0265e00c |
| 24-Oct-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: Add rk3576 clock driver
Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.
- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk set
clk: rockchip: Add rk3576 clock driver
Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.
- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk setting rule
- relase bigcore biu\cru\grf in spl
- add ufs ref clk setting
- Remove PCIe relevant
- fix hdmi phy name
- add dsihost and ebc clk setting
- add dsihot getting
- fix dclk getting freq error
Change-Id: I2658bf3f77f6386a6f124f624a0658d61cf90fc2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
show more ...
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