| #
5e016f25 |
| 17-Jan-2024 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3528: Add cpu pvtpll support for SPL
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I75647ab4f194883779db866748a727d4011d1c0f
|
| #
ffe7a059 |
| 07-Sep-2023 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
clk: fix compile error with usbplug config
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I3776bb5bebc43857b38bbc4933aa5b584ffc97f6
|
| #
8da8d76a |
| 22-Feb-2023 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: rk3528: Avoid 200m_src and 300m_src overclocking when change gpll rate
Change-Id: Ib538d742545b91a4e772dbc8b6e9d3a90cd50e19
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Sig
clk: rockchip: rk3528: Avoid 200m_src and 300m_src overclocking when change gpll rate
Change-Id: Ib538d742545b91a4e772dbc8b6e9d3a90cd50e19
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
show more ...
|
| #
08bd15b0 |
| 23-Feb-2023 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Fix aclk_m_core register
Bootrom set the aclk_m_core_div=0 and SPL set cpu rate 600M,
so the aclk_m_core is 600M which overs the sign-off rate 550M
a little.
U-Boot use scmi
clk: rockchip: rk3528: Fix aclk_m_core register
Bootrom set the aclk_m_core_div=0 and SPL set cpu rate 600M,
so the aclk_m_core is 600M which overs the sign-off rate 550M
a little.
U-Boot use scmi clk to set high cpu rate which updates aclk_m_core_div
to corresponding value, it's safe.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If5def6af30be417f5dbebdf416c2d9da7655520c
show more ...
|
| #
af1a0c68 |
| 15-Feb-2023 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Fix matrix 339M freq set/get error
The freq is set to 475.2M by mistake, it makes eMMC work abnormally.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I1d14717
clk: rockchip: rk3528: Fix matrix 339M freq set/get error
The freq is set to 475.2M by mistake, it makes eMMC work abnormally.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I1d14717970a194fb2f1c4062fb7aaf8b71a0a39e
show more ...
|
| #
68ba0295 |
| 10-Feb-2023 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Add scmi clk for SPL to handle crypto
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I03709dc3e90031240a09753bcceaee32dbe7cc5f
|
| #
e855752a |
| 16-Jan-2023 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: clean coding style
Macro name style follows the other platform.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Icd0db5c113ddf9e9e8172f2585ce9806f23d3cc2
|
| #
eee09e1f |
| 02-Dec-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Init matrix clocks in SPL
Init them to override bootrom config, otherwise we get unexpected
matrix rate:
clk_200m 396000 KHz
clk_300m 594000 KHz
clk_339m 264000 KHz
Signed-o
clk: rockchip: rk3528: Init matrix clocks in SPL
Init them to override bootrom config, otherwise we get unexpected
matrix rate:
clk_200m 396000 KHz
clk_300m 594000 KHz
clk_339m 264000 KHz
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I77f257895961c30db8543bfc7ca2d161b263a1ef
show more ...
|
| #
3aaac136 |
| 02-Dec-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Fix get spi clock
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I60a88fd6814e2cd9053adea0b30a13f8b3d6364e
|
| #
161d3423 |
| 30-Nov-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Use pvtpll for cpu rate
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie3a117359e7aca5d30d3296a21ea0605ae23f362
|
| #
1a259ed3 |
| 30-Nov-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Init PPLL 1000MHZ
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ife9bdab0023e3ee76d8f3930569fb9d6b119125b
|
| #
333ce117 |
| 30-Nov-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: invoke .set_parent() for dclk0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6be0293d97fa0de0b2ca06ab45de1e6407f818be
|
| #
9d012e64 |
| 29-Nov-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Fix dclk_vop0/1
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9ad54c30e3c6200686cc19be6c4581d5a1991f91
|
| #
a9533156 |
| 29-Nov-2022 |
Joseph Chen <chenjh@rock-chips.com> |
clk: rockchip: rk3528: Add gmac1 50M/125M set rate
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5ca30870d1d4196fa3fb2a87ddb7035e19c76472
|
| #
c6f7c1a3 |
| 18-Aug-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: Add rk3528 support
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I0683071e9bdde1cb5aa4c3df40750f33a3faa85b
|