272 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)  in rockchip_get_pll_settings()  argument
276 	while (rate_table->rate) {  in rockchip_get_pll_settings()
277 		if (rate_table->rate == rate)  in rockchip_get_pll_settings()
281 	if (rate_table->rate != rate) {  in rockchip_get_pll_settings()
283 			return rk3588_pll_clk_set_by_auto(24 * MHZ, rate);  in rockchip_get_pll_settings()
285 			return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);  in rockchip_get_pll_settings()
295 	const struct rockchip_pll_rate_table *rate;  in rk3036_pll_set_rate()  local
298 	rate = rockchip_get_pll_settings(pll, drate);  in rk3036_pll_set_rate()
299 	if (!rate) {  in rk3036_pll_set_rate()
305 	      __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv);  in rk3036_pll_set_rate()
307 	      __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);  in rk3036_pll_set_rate()
326 		     (rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |  in rk3036_pll_set_rate()
327 		     rate->fbdiv);  in rk3036_pll_set_rate()
331 		     (rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |  in rk3036_pll_set_rate()
332 		     rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));  in rk3036_pll_set_rate()
335 			     rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);  in rk3036_pll_set_rate()
336 	if (!rate->dsmpd) {  in rk3036_pll_set_rate()
339 			    (rate->frac << RK3036_PLLCON2_FRAC_SHIFT),  in rk3036_pll_set_rate()
375 	ulong rate, p_rate = OSC_HZ / KHZ;  in rk3036_pll_get_rate()  local
407 		rate = (p_rate * fbdiv / (refdiv * postdiv1 * postdiv2)) * KHZ;  in rk3036_pll_get_rate()
415 			rate += frac_rate;  in rk3036_pll_get_rate()
417 		return rate;  in rk3036_pll_get_rate()
448 	const struct rockchip_pll_rate_table *rate;  in rk3588_pll_set_rate()  local
450 	rate = rockchip_get_pll_settings(pll, drate);  in rk3588_pll_set_rate()
451 	if (!rate) {  in rk3588_pll_set_rate()
457 	      __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);  in rk3588_pll_set_rate()
488 		     (rate->m << RK3588_PLLCON0_M_SHIFT));  in rk3588_pll_set_rate()
492 		     (rate->p << RK3588_PLLCON1_P_SHIFT |  in rk3588_pll_set_rate()
493 		     rate->s << RK3588_PLLCON1_S_SHIFT));  in rk3588_pll_set_rate()
497 		     rate->k << RK3588_PLLCON2_K_SHIFT);  in rk3588_pll_set_rate()
566 	u64 rate, postdiv;  in rk3588_pll_get_rate()  local
591 		rate = OSC_HZ / p;  in rk3588_pll_get_rate()
592 		rate *= m;  in rk3588_pll_get_rate()
602 			rate -= frac_rate64;  in rk3588_pll_get_rate()
610 			rate += frac_rate64;  in rk3588_pll_get_rate()
612 		rate = rate >> s;  in rk3588_pll_get_rate()
613 		return rate;  in rk3588_pll_get_rate()
624 	ulong rate = 0;  in rockchip_pll_get_rate()  local
629 		rate = rk3036_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
633 		rate = rk3036_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
637 		rate = rk3588_pll_get_rate(pll, base, pll_id);  in rockchip_pll_get_rate()
643 	return rate;  in rockchip_pll_get_rate()
677 			  ulong rate)  in rockchip_get_cpu_settings()  argument
681 	while (ps->rate) {  in rockchip_get_cpu_settings()
682 		if (ps->rate == rate)  in rockchip_get_cpu_settings()
686 	if (ps->rate != rate)  in rockchip_get_cpu_settings()