clk: rockchip: rk3128: Fix error return for SPI

Change-Id: Ie65192989fb83ec5b2a5c742144091d6b9df2274
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

clk: rockchip: rk3128: add support to set and get spi clock

Change-Id: I4ac874ba0542474baf18491f986f401c831a5ad4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3128: support crypto clk get/set rate

Change-Id: I3a7d71a481aca04c9e6c0547cfc05a8106f79423
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3128: support pclk_wdt get rate

Change-Id: Ie5dbfe5bd3fdd7868a5db64b96471a5524bde462
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3128: print arm enter and init rate

Change-Id: I0be1752522a83a2d111870e5a8ac95f92bd7f9a5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk312x: add sfc clk init

Change-Id: I5edf0a4b650a57a48f837fa3e007cfaf6a733f92
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>

clk: rockchip: rk312x: add cpll freq init

Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop displ

clk: rockchip: rk312x: add cpll freq init

Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop display, the cpll need to set init freq for other
children clk.

Change-Id: Ia45892dd3c8efb77cf32b631329d927aceb8dd86
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: mmc: add mmc set and get phase

add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chi

clk: rockchip: mmc: add mmc set and get phase

add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk3128: support more clks to set and get rate

Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.

Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e

rockchip: clk: rk3128: support more clks to set and get rate

Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.

Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e3e42bc08
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk3128: add ofdata_to_platdata callback

We need to init platdata from of data with ofdata_to_platdata callback.

Change-Id: I9e8e9427767f9de84c9871d9a639e7fdb5319ba4
Signed-off-by: Ke

rockchip: clk: rk3128: add ofdata_to_platdata callback

We need to init platdata from of data with ofdata_to_platdata callback.

Change-Id: I9e8e9427767f9de84c9871d9a639e7fdb5319ba4
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clk: rk3128: convert to live dt

Change-Id: I54752b7037cda13eb0f7efbc515291fc944fad41
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: clk: add compatible for rk3126

kernel dts may use rk3126 or rk3128, sync it to work with kernel dtb.

Change-Id: Id582f403605d3be16ab53f6088f576d90ed5bd1e
Signed-off-by: Kever Yang <kever.

rockchip: clk: add compatible for rk3126

kernel dts may use rk3126 or rk3128, sync it to work with kernel dtb.

Change-Id: Id582f403605d3be16ab53f6088f576d90ed5bd1e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clk: rk3128: update hclk/pclk assert

Update assert compare target, we use BUS_ACLK_HZ instead of GPLL

Change-Id: Ic5acf6f2045e9db45523f2468df74119eb8f23e2
Signed-off-by: Kever Yang <kever

rockchip: clk: rk3128: update hclk/pclk assert

Update assert compare target, we use BUS_ACLK_HZ instead of GPLL

Change-Id: Ic5acf6f2045e9db45523f2468df74119eb8f23e2
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: Use common interface for pclk_peri

The peripherals pclk rate is the same, use a common interface
for peripherals like i2c, pwm and etc.

Change-Id: Id9668400f2bb24be397adee312da5365e0

clk: rockchip: Use common interface for pclk_peri

The peripherals pclk rate is the same, use a common interface
for peripherals like i2c, pwm and etc.

Change-Id: Id9668400f2bb24be397adee312da5365e09c9237
Signed-off-by: David Wu <david.wu@rock-chips.com>

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rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.co

rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: rk3128: support dclk_lcdc and aclk_vio setting

support vop clk setting freq, for uboot logo display.

Change-Id: I766bdc2c3a13d0ee92f81fbd7a30b7cc87c2dceb
Signed-off-by: Elaine Zhang

clk: rockchip: rk3128: support dclk_lcdc and aclk_vio setting

support vop clk setting freq, for uboot logo display.

Change-Id: I766bdc2c3a13d0ee92f81fbd7a30b7cc87c2dceb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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3128: clock: config nand controller working clock max 150Mhz

nandc working clock div from gpll and max clock config 150Mhz
while gpll config as 600Mhz.

Change-Id: I893d453d031a0ddd0cd79111699d36000

3128: clock: config nand controller working clock max 150Mhz

nandc working clock div from gpll and max clock config 150Mhz
while gpll config as 600Mhz.

Change-Id: I893d453d031a0ddd0cd79111699d3600095c6e4f
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

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clk: rockchip: Add rk3128 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I973

clk: rockchip: Add rk3128 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I973b5f50b81559f054ca552ab69ec176cbe3abaa
Signed-off-by: David Wu <david.wu@rock-chips.com>

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clk: rockchip: rk3128: support i2c clk get and set rate

Change-Id: I16af8297918b677165244330a4a39d3f041d5ee4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: rk3128: add clock driver

Add rk3128 clock driver and cru structure definition.

Change-Id: Ib6e17f56b2e7e6cc6cdf06f8d9ac44c062b5b6e3
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>