clk: rockchip: rk3588: add 1150M for pll table

Change-Id: I0592228084cd4ad223333413c5e132169f205d82
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rk3588: Init the PPLL to 1.1G by default

The initialization frequency of PPLL needs to be consistent with
the kernel to avoid modifying PPLL when loading kernel DTB,
which may cause abnormal re

clk: rk3588: Init the PPLL to 1.1G by default

The initialization frequency of PPLL needs to be consistent with
the kernel to avoid modifying PPLL when loading kernel DTB,
which may cause abnormal reference clock of SATA.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icc7bdaf7aa78bde645dc81e3b709a78dd02a552c

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clk: rockchip: Add rk3576 clock driver

Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.

- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk set

clk: rockchip: Add rk3576 clock driver

Add basic clock for rk3576 which including cpu, mmc, i2c,
pwm ...clocks init.

- init spll\ppll\cpll\cci in spl
- fix cci init
- fix up spll
- fix the dclk setting rule
- relase bigcore biu\cru\grf in spl
- add ufs ref clk setting
- Remove PCIe relevant
- fix hdmi phy name
- add dsihost and ebc clk setting
- add dsihot getting
- fix dclk getting freq error

Change-Id: I2658bf3f77f6386a6f124f624a0658d61cf90fc2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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clk: rockchip: match the kernel dclk clock scheme

Change-Id: I6082edbb3147b59029812c53f03598988cb62b54
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: fix compile error with usbplug config

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I3776bb5bebc43857b38bbc4933aa5b584ffc97f6

clk: rockchip: rk3588: Avoid re-setting the pll rate of dclk_vop's parent

Change-Id: I9d250bdf2346789f81507b7dfe204fbede6c8ac4
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

clk: rockchip: rk3588: support aclk_top_root set 750M

Change-Id: I78f00d37a645f37e28587d1c31f3179d5fa891e7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rk3588: Add 742.5M parameter for PLL

Change-Id: I5a842a3103df9a566789e7635fb484e4bb0bf427
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>

clk: rockchip: rk3588: fix unsigned compared against 0

Change-Id: I4e2e5a8a4524c2be2b53b8cea95f39d1d270a68b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: rk3588: do coding style

Fix identical code for different branches.

Change-Id: Idd15347d5367bc4a3165046c23fb6e8ff0694fd9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: rk3588: remove dead code

Change-Id: I1aa718b3ff637467321f05ae80eddd85a20bfc7b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: rk3588: do memset for clk structure

Change-Id: I229093ad350787fa60334b50ae9e4f48144bd46f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: rk3588: fix copy-paster error

Change-Id: If3b2ce36f4f26530cf78c92bcfb01df8b4f63f09
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

clk: rockchip: rk3588: change cpul clock source to pvtpll

Change-Id: I4ab6d15c05b4cb805b60125cb5bb7e7d2e65d6e5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rk3588: add wdt clk

Change-Id: I74634dc216b09400c1abe3fbf42106accf9f0108
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rk3588: Init the PPLL to 1.1G

The pcie2 combophy clk output will have better quality in this setting.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780

clk: rk3588: Init the PPLL to 1.1G

The pcie2 combophy clk output will have better quality in this setting.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I9e312123a51d7f34c6c22780148f63d14c147442

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clk: rk3588: Add 1.1G parameter for PLL

PPLL may need to use 1.1G Hz.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I81a86e0fe47c88a0aefced6502723a8469ec59e0

clk: rockchip: rk3588: fix up clk_pwm1 setting error

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I391357118f8f0c5fd55703ae9aaa27d64d63b173

clk: rockchip: rk3588: support setting dp aux channel clk

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I65954d0805ce51c042dd5ca469781fb55ab1bccc

clk: rockchip: rk3588: set b0pll b1pll to 1200M in SPL

Change-Id: Idc47b57e940da7d9c4deeceba004bc5fc8d6c2ad
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3588: Identify the dclk's parent by device name

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I6cb07de419eb0702a2b4445a059f96a44b7856c8

clk: rockchip: rk3588: fix up dclk_vop3 setting error

Change-Id: I345a254f9adaf44d6dcd2bf37b4f429676643e44
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3588: Support hdmiphy pll

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4fa787ed2b6057579985ab8469adef888eee1ee7

clk: rockchip: rk3588: support aclk_vop to 850M

Change-Id: I1a42434e63e6fb6d55dc80827304e2c78ef3dcf1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3588: Use scmi clk for cpub

Change-Id: Iac761088bd65d14f906fb0fe212d307b00f5d6c7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>