clk: rockchip: px30 set i2s1 mclk out rate to 11289600 Hz

The px30 i2s1 mclk default to source from gpll, it may outputs 100 MHz
when the gpll rate up to 1200MHz. Some slave codec may fail to work a

clk: rockchip: px30 set i2s1 mclk out rate to 11289600 Hz

The px30 i2s1 mclk default to source from gpll, it may outputs 100 MHz
when the gpll rate up to 1200MHz. Some slave codec may fail to work at
the high frequency.

This patch will set the i2s1 mclk source from xin_osc_half before gpll
rate up, and then set to 11289600 Hz after gpll rate up.

Change-Id: I2a7641ed7c0db794e50aaacbbc6bb361a8b5db72
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

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clk: rockchip: px30: add otp clk and support px30s

Change-Id: I4e16a4e28a25ce3897a368a35da560faf8264640
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: support crypto clock in spl

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I68498fc96d244eb9eafda1baa2ca74ef72d27727

clk/rockchip: px30: support any frequency for i2s1_mclk

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ica0ca19d1a4fafbaf62e5c789ae3223ff9d86632

clk: rockchip: px30: fix n/m for sclk_i2s1

High 16-bit for numerator, Low 16-bit for denominator.

Fixes: 95f2641240fb ("clk: rockchip: px30: add support clock for SCLK_I2S1")
Signed-off-by: Wyon Bi

clk: rockchip: px30: fix n/m for sclk_i2s1

High 16-bit for numerator, Low 16-bit for denominator.

Fixes: 95f2641240fb ("clk: rockchip: px30: add support clock for SCLK_I2S1")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Iafbb03ceaa7ccc178ee2a74be2fab6c2b7268ced

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Merge branch 'next-dev' into thunder-boot

clk: rockchip: px30: Restore sfc frequency after PLL frequency setting

Change-Id: I261885b027c4c5ba6d94fb228fb04563cb4e0b0e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: add mac clk interface

support mac clk set rate and set parent.

Change-Id: Iaadcb701cf37083d90a37b24f4ffba3bef9c88cd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: support pclk_wdt get rate

Change-Id: I1d58d032c6f3843df3fdee65b1ee9cd3614435b1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: print arm enter and init rate

Change-Id: I0d2a1c6bb92397210314322fd147c4a8a6e81abd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: modify the dclk divider to even

When DCLK use CPLL alone, the DCLK timing is critical value.
The odd-divider spacing ratio is not 50%,
it will affect the setup time of the displ

clk: rockchip: px30: modify the dclk divider to even

When DCLK use CPLL alone, the DCLK timing is critical value.
The odd-divider spacing ratio is not 50%,
it will affect the setup time of the display.
Therefore, it is suggested that we use even-divider
to make the spacing ratio is 50%.

Change-Id: I07c0fd57dd1f27984f8186f1d7c2f96df2ea10a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: px30: support setting clk_i2s_out_mclk to 12MHz

Change-Id: I53fb5ceac0c423dd90c493d6f05069569c839f4e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

clk: rockchip: px30: support crypto clk setting

Change-Id: I9971fb2b6a40640d78fb259c72aac32582f8e90d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: support arm clk 408M

Change-Id: I98cd856c99ebf2cd77d1a8ff94d2e0a40f0a4bfb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

clk: rockchip: support clk_tsadc setting freq

Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: px30: add support clock for SCLK_I2S1

Change-Id: Iaaacd6fdabe2c702202ffe09dc95cd6d648597d6
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

rockchip: clk: px30: Add support to initialize npll rate

Change-Id: If98ed54ad785a40efae7da78c5f0122158a3de61
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add support to get vopl aclk and dclk

Change-Id: Id40cbddf780889e308839b7beb2cfb894d407914
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add px30_clk_init()

Add support to initialize gpll, bus and peri clock rate.

Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-c

rockchip: clk: px30: Add px30_clk_init()

Add support to initialize gpll, bus and peri clock rate.

Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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rockchip: clk: px30: Add support to set vopl aclk and dclk rate

Change-Id: I31376ebb8d1d40d46ad4e2b6421b65ac7fae096d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add support to limit minimum rate for vop dclk

Change-Id: Ieff359603b1b6dede4377b1a17daf3eb803e2552
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Avoid setting gpll rate repeatedly

Change-Id: I24a062bf17f2552b94c9421b52ee930890fefcb6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: restore bus and peri rate when change gpll rate

Change-Id: I208196e11e7c4fa5db26a02abdd41ecfa610d5bd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add support to set npll rate

Change-Id: Ida62e70610bd28d4c7d327e0431f09b0e4de6b2e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: px30: Add clk_set_defaults()

As clk_set_defaults() is removed in device core, so add it in clock
driver.

Change-Id: Ib5b9a7f81c738c65f2cb3e0ca74a410cda2ca1e2
Signed-off-by: Finley Xi

rockchip: clk: px30: Add clk_set_defaults()

As clk_set_defaults() is removed in device core, so add it in clock
driver.

Change-Id: Ib5b9a7f81c738c65f2cb3e0ca74a410cda2ca1e2
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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