clk: rockchip: rv1126: Add support for micsi out clk

It's essential to configure vccio4's io_vsel and iomux before clk
setting.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ib

clk: rockchip: rv1126: Add support for micsi out clk

It's essential to configure vccio4's io_vsel and iomux before clk
setting.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ibb404453d4f9218e4ccec1cc8d800d95f8bccda4

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clk: rockchip: rv1126: mux aclk_pdbus according to frequency

Aim to reduce power consumption, cpll should be gated and the clocks
will mux to non-cpll.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.c

clk: rockchip: rv1126: mux aclk_pdbus according to frequency

Aim to reduce power consumption, cpll should be gated and the clocks
will mux to non-cpll.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: If9d1b48cdb237cf38133523a4fc20fa6e87e8e62

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clk: rockchip: rv1126: support wdt clk set/get rate

Change-Id: If47a22130507cb3512a8f19b474ea1e01354b52b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rv1126: Fix mask bits for gmac src clks

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7f81a3e7586dcb85511502d3a329ac1cba7ccc8a

clk: rockchip: rv1126: always support decompress clock get/set

The SPL without thunder-boot or U-Boot needs it.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie2d8b59e35fbc2056cfbc9

clk: rockchip: rv1126: always support decompress clock get/set

The SPL without thunder-boot or U-Boot needs it.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie2d8b59e35fbc2056cfbc910dae94419afcbfc09

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clk: rockchip: rv1126: Add support to get dpll rate

Change-Id: Icd7c40235d4627befc216812bfdcb288790e63e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Change pclk pdbus parent to gpll

As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent

clk: rockchip: rv1126: Change pclk pdbus parent to gpll

As dmac aclk comes from hclk pdbus, dmac pclk comes frome pclk pdbus,
dmac aclk should be an integer multiple of dmac pclk and the same
parent with dmac pclk. so let hclk pdbus and pclk pdbus only come from
gpll.

Change-Id: Idd2f362fcf160352dcb4577ad8a13b4dbec7c65f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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clk: rockchip: rv1126: Add clock init for isp and vop

Change-Id: I1c4a1267e90f84f6f7777a35e0ad5824b6eff2d1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Add support for decom clock

Change-Id: I90eacb03ed191b804911429af5ad80daab3776cc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Add support for isp and ispp clocks

Change-Id: Icfd87f56c30bfa81b6e7fecadcda090c26a8c465
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Merge branch 'thunder-boot' into next-dev

clk: rockchip: rv1126: Add support for gmac

Change-Id: I10ade6acbbfe5dd23e33a250ef601948606bc57e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Fix CLK_SCR1_CORE return error

Change-Id: I4938dd5519dde3a5357b5daf398d5915976ce74e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Add PLL configuration for 1400MHz

The rate of HPLL is 1400MHz.

Change-Id: I225017f7fb461124c74939828aee4a2a40222097
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Add support to init hpll and 32k

Change-Id: If41a708d925c978e8db1e21b23c16d9a9a2e29d8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Modify divs for pll

There are some constraints for pll.
Input frequency range(Int): 5MHz to 1200MHz.
Input frequency range(Frac): 10MHz to 1200MHz.
Output frequency range: 16M

clk: rockchip: rv1126: Modify divs for pll

There are some constraints for pll.
Input frequency range(Int): 5MHz to 1200MHz.
Input frequency range(Frac): 10MHz to 1200MHz.
Output frequency range: 16MHz to 6400MHz.
VCO frequency range: 1600MHz to 6400MHz.
Feedback divide(Int): 16 t0 640.
Feedback divide(Frac): 20 to 320.
Postdiv1 >= Postdiv2.

Change-Id: Ic8b8da6097f476597733984145056b6cc6cc453e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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clk: rockchip: rv1126: Change CPLL to 500MHz

Make clk_gmac_ethernet_out2io 25MHz comes from CPLL.

Change-Id: Ie7f3bf457db8f92a5d75a0e5a78e5e61ffc7b0ac
Signed-off-by: Finley Xiao <finley.xiao@rock-c

clk: rockchip: rv1126: Change CPLL to 500MHz

Make clk_gmac_ethernet_out2io 25MHz comes from CPLL.

Change-Id: Ie7f3bf457db8f92a5d75a0e5a78e5e61ffc7b0ac
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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clk: rockchip: rv1126: Add support for SCR1

Change-Id: I22f0cea9ab0612250ab41526684dc3d786555a37
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Change some clocks' parent to GPLL

Change-Id: Ibba02fee3df6c98308d5fd657a30af3eba7321d5
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Fix HCLK_PDPHP_DIV_SHIFT

Change-Id: Ia30bcf94de7ee3e40359fdd47d4e8c6600f4559d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Don't restore clk when gpll is default 24MHz

Change-Id: Ie7b2609078ae1b68fb8e081b4064381e3dbb36a8
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Fix gpll_hz is zero when set gpll clk

Change-Id: Iecd64e83d2a841b711c80528a245d2e9bda11265
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Remove unused local variable ret

Change-Id: I2c4a056fd9fac2b50fd55a529133f7ea6f394437
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Add support restore emmc/sfc/nandc frequency

Change-Id: Iaa62eead12156d284a6ee315dfbaf92e786a0920
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: rv1126: Add support for sfc and nandc

Change-Id: Ifb6873bf417adaaf95703064deeaed54b890b20b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>