Lines Matching refs:rate
63 .rate = _rate##U, \
157 const struct rockchip_cpu_rate_table *rate; in rk3562_armclk_set_rate() local
161 rate = rockchip_get_cpu_settings(rk3562_cpu_rates, new_rate); in rk3562_armclk_set_rate()
162 if (!rate) { in rk3562_armclk_set_rate()
174 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
176 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
183 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
185 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
189 rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
191 rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT); in rk3562_armclk_set_rate()
206 ulong rate; in rk3562_bus_get_rate() local
229 rate = priv->cpll_hz; in rk3562_bus_get_rate()
231 rate = priv->gpll_hz; in rk3562_bus_get_rate()
233 return DIV_TO_RATE(rate, div); in rk3562_bus_get_rate()
237 ulong rate) in rk3562_bus_set_rate() argument
242 if (priv->cpll_hz % rate == 0) { in rk3562_bus_set_rate()
244 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_bus_set_rate()
247 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_bus_set_rate()
280 ulong rate; in rk3562_peri_get_rate() local
303 rate = priv->cpll_hz; in rk3562_peri_get_rate()
305 rate = priv->gpll_hz; in rk3562_peri_get_rate()
307 return DIV_TO_RATE(rate, div); in rk3562_peri_get_rate()
311 ulong rate) in rk3562_peri_set_rate() argument
316 if (priv->cpll_hz % rate == 0) { in rk3562_peri_set_rate()
318 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_peri_set_rate()
321 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_peri_set_rate()
354 ulong rate; in rk3562_i2c_get_rate() local
361 rate = 200 * MHz; in rk3562_i2c_get_rate()
363 rate = OSC_HZ; in rk3562_i2c_get_rate()
365 rate = 32768; in rk3562_i2c_get_rate()
368 return DIV_TO_RATE(rate, div); in rk3562_i2c_get_rate()
378 rate = 200 * MHz; in rk3562_i2c_get_rate()
380 rate = 100 * MHz; in rk3562_i2c_get_rate()
382 rate = 50 * MHz; in rk3562_i2c_get_rate()
384 rate = OSC_HZ; in rk3562_i2c_get_rate()
390 return rate; in rk3562_i2c_get_rate()
394 ulong rate) in rk3562_i2c_set_rate() argument
401 if (rate == 200 * MHz) { in rk3562_i2c_set_rate()
404 } else if (rate == OSC_HZ) { in rk3562_i2c_set_rate()
407 } else if (rate == 32768) { in rk3562_i2c_set_rate()
412 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_i2c_set_rate()
425 if (rate == 200 * MHz) in rk3562_i2c_set_rate()
427 else if (rate == 100 * MHz) in rk3562_i2c_set_rate()
429 else if (rate == 50 * MHz) in rk3562_i2c_set_rate()
522 ulong rate) in rk3562_uart_set_rate() argument
530 if (priv->cpll_hz % rate == 0) { in rk3562_uart_set_rate()
532 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_uart_set_rate()
533 } else if (rate == OSC_HZ) { in rk3562_uart_set_rate()
539 rational_best_approximation(rate, priv->cpll_hz / div, in rk3562_uart_set_rate()
587 if (priv->gpll_hz % rate == 0) { in rk3562_uart_set_rate()
590 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_uart_set_rate()
591 } else if (priv->cpll_hz % rate == 0) { in rk3562_uart_set_rate()
594 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_uart_set_rate()
595 } else if (rate == OSC_HZ) { in rk3562_uart_set_rate()
603 rational_best_approximation(rate, priv->gpll_hz / div, in rk3562_uart_set_rate()
627 ulong rate; in rk3562_pwm_get_rate() local
634 rate = 200 * MHz; in rk3562_pwm_get_rate()
636 rate = OSC_HZ; in rk3562_pwm_get_rate()
638 rate = 32768; in rk3562_pwm_get_rate()
641 return DIV_TO_RATE(rate, div); in rk3562_pwm_get_rate()
661 rate = 100 * MHz; in rk3562_pwm_get_rate()
663 rate = 50 * MHz; in rk3562_pwm_get_rate()
665 rate = OSC_HZ; in rk3562_pwm_get_rate()
667 return rate; in rk3562_pwm_get_rate()
671 ulong rate) in rk3562_pwm_set_rate() argument
678 if (rate == 200 * MHz) { in rk3562_pwm_set_rate()
681 } else if (rate == OSC_HZ) { in rk3562_pwm_set_rate()
684 } else if (rate == 32768) { in rk3562_pwm_set_rate()
689 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_pwm_set_rate()
714 if (rate == 100 * MHz) in rk3562_pwm_set_rate()
716 else if (rate == 50 * MHz) in rk3562_pwm_set_rate()
729 ulong rate; in rk3562_spi_get_rate() local
736 rate = 200 * MHz; in rk3562_spi_get_rate()
738 rate = OSC_HZ; in rk3562_spi_get_rate()
740 rate = 32768; in rk3562_spi_get_rate()
743 return DIV_TO_RATE(rate, div); in rk3562_spi_get_rate()
759 rate = 200 * MHz; in rk3562_spi_get_rate()
761 rate = 100 * MHz; in rk3562_spi_get_rate()
763 rate = 50 * MHz; in rk3562_spi_get_rate()
765 rate = OSC_HZ; in rk3562_spi_get_rate()
767 return rate; in rk3562_spi_get_rate()
771 ulong rate) in rk3562_spi_set_rate() argument
778 if (rate == 200 * MHz) { in rk3562_spi_set_rate()
781 } else if (rate == OSC_HZ) { in rk3562_spi_set_rate()
784 } else if (rate == 32768) { in rk3562_spi_set_rate()
789 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_spi_set_rate()
810 if (rate == 200 * MHz) in rk3562_spi_set_rate()
812 else if (rate == 100 * MHz) in rk3562_spi_set_rate()
814 else if (rate == 50 * MHz) in rk3562_spi_set_rate()
845 ulong rate) in rk3562_tsadc_set_rate() argument
863 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_tsadc_set_rate()
892 ulong rate) in rk3562_saradc_set_rate() argument
899 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_saradc_set_rate()
904 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_saradc_set_rate()
933 static ulong rk3562_sfc_set_rate(struct rk3562_clk_priv *priv, ulong rate) in rk3562_sfc_set_rate() argument
938 if (OSC_HZ % rate == 0) { in rk3562_sfc_set_rate()
939 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_sfc_set_rate()
941 } else if ((priv->cpll_hz % rate) == 0) { in rk3562_sfc_set_rate()
942 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_sfc_set_rate()
945 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_sfc_set_rate()
994 ulong rate) in rk3562_emmc_set_rate() argument
1001 if (OSC_HZ % rate == 0) { in rk3562_emmc_set_rate()
1002 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_emmc_set_rate()
1004 } else if ((priv->cpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1005 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_emmc_set_rate()
1007 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1008 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_emmc_set_rate()
1011 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_emmc_set_rate()
1020 if ((priv->cpll_hz % rate) == 0) { in rk3562_emmc_set_rate()
1021 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_emmc_set_rate()
1024 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_emmc_set_rate()
1077 ulong clk_id, ulong rate) in rk3562_sdmmc_set_rate() argument
1082 if (OSC_HZ % rate == 0) { in rk3562_sdmmc_set_rate()
1083 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3562_sdmmc_set_rate()
1085 } else if ((priv->cpll_hz % rate) == 0) { in rk3562_sdmmc_set_rate()
1086 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_sdmmc_set_rate()
1088 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_sdmmc_set_rate()
1089 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_sdmmc_set_rate()
1092 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_sdmmc_set_rate()
1174 ulong rate) in rk3562_vop_set_rate() argument
1182 if ((priv->cpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1183 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_vop_set_rate()
1185 } else if ((priv->hpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1186 div = DIV_ROUND_UP(priv->hpll_hz, rate); in rk3562_vop_set_rate()
1188 } else if ((priv->vpll_hz % rate) == 0) { in rk3562_vop_set_rate()
1189 div = DIV_ROUND_UP(priv->vpll_hz, rate); in rk3562_vop_set_rate()
1192 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_vop_set_rate()
1202 div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate); in rk3562_vop_set_rate()
1210 VPLL, div * rate); in rk3562_vop_set_rate()
1229 div = DIV_ROUND_UP(pll_rate, rate); in rk3562_vop_set_rate()
1233 if (abs(rate - now) < abs(rate - best_rate)) { in rk3562_vop_set_rate()
1247 printf("do not support this vop freq %lu\n", rate); in rk3562_vop_set_rate()
1303 ulong rate) in rk3562_gmac_set_rate() argument
1310 if (rate == 125000000) in rk3562_gmac_set_rate()
1318 if (rate == 50000000) in rk3562_gmac_set_rate()
1326 if (rate == 50000000) in rk3562_gmac_set_rate()
1334 if ((priv->cpll_hz % rate) == 0) { in rk3562_gmac_set_rate()
1335 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_gmac_set_rate()
1338 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_gmac_set_rate()
1356 ulong rate = 0; in rk3562_clk_get_rate() local
1367 rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru, in rk3562_clk_get_rate()
1371 rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru, in rk3562_clk_get_rate()
1376 rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru, in rk3562_clk_get_rate()
1380 rate = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_get_rate()
1384 rate = rockchip_pll_get_rate(&rk3562_pll_clks[CPLL], priv->cru, in rk3562_clk_get_rate()
1388 rate = rockchip_pll_get_rate(&rk3562_pll_clks[DPLL], priv->cru, in rk3562_clk_get_rate()
1394 rate = rk3562_bus_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1399 rate = rk3562_peri_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1408 rate = rk3562_i2c_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1420 rate = rk3562_uart_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1426 rate = rk3562_pwm_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1431 rate = rk3562_spi_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1435 rate = rk3562_tsadc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1439 rate = rk3562_saradc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1442 rate = rk3562_sfc_get_rate(priv); in rk3562_clk_get_rate()
1446 rate = rk3562_emmc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1454 rate = rk3562_sdmmc_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1459 rate = rk3562_vop_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1465 rate = rk3562_gmac_get_rate(priv, clk->id); in rk3562_clk_get_rate()
1468 rate = OSC_HZ; in rk3562_clk_get_rate()
1474 return rate; in rk3562_clk_get_rate()
1477 static ulong rk3562_clk_set_rate(struct clk *clk, ulong rate) in rk3562_clk_set_rate() argument
1488 debug("%s: id=%ld, rate=%ld\n", __func__, clk->id, rate); in rk3562_clk_set_rate()
1494 rk3562_armclk_set_rate(priv, rate); in rk3562_clk_set_rate()
1495 priv->armclk_hz = rate; in rk3562_clk_set_rate()
1499 GPLL, rate); in rk3562_clk_set_rate()
1505 VPLL, rate); in rk3562_clk_set_rate()
1511 HPLL, rate); in rk3562_clk_set_rate()
1518 ret = rk3562_bus_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1523 ret = rk3562_peri_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1532 ret = rk3562_i2c_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1544 ret = rk3562_uart_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1550 ret = rk3562_pwm_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1555 ret = rk3562_spi_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1559 ret = rk3562_tsadc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1563 ret = rk3562_saradc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1566 ret = rk3562_sfc_set_rate(priv, rate); in rk3562_clk_set_rate()
1570 ret = rk3562_emmc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1576 ret = rk3562_sdmmc_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1581 ret = rk3562_vop_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1587 ret = rk3562_gmac_set_rate(priv, clk->id, rate); in rk3562_clk_set_rate()
1615 ulong rate; in rk3562_mmc_get_phase() local
1617 rate = rk3562_clk_get_rate(clk); in rk3562_mmc_get_phase()
1618 if (rate < 0) in rk3562_mmc_get_phase()
1619 return rate; in rk3562_mmc_get_phase()
1634 36 * (rate / 1000000); in rk3562_mmc_get_phase()
1650 ulong rate; in rk3562_mmc_set_phase() local
1652 rate = rk3562_clk_get_rate(clk); in rk3562_mmc_set_phase()
1653 if (rate < 0) in rk3562_mmc_set_phase()
1654 return rate; in rk3562_mmc_set_phase()
1665 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3562_mmc_set_phase()
1738 ulong rate; in soc_clk_dump() local
1764 rate = clk_get_rate(&clk); in soc_clk_dump()
1767 if (rate < 0) in soc_clk_dump()
1772 rate / 1000); in soc_clk_dump()
1774 if (rate < 0) in soc_clk_dump()
1779 rate / 1000); in soc_clk_dump()
1931 ulong rate; in rk3562_crypto_get_rate() local
1939 rate = 200 * MHz; in rk3562_crypto_get_rate()
1941 rate = 100 * MHz; in rk3562_crypto_get_rate()
1943 rate = OSC_HZ; in rk3562_crypto_get_rate()
1949 rate = 300 * MHz; in rk3562_crypto_get_rate()
1951 rate = 200 * MHz; in rk3562_crypto_get_rate()
1953 rate = 100 * MHz; in rk3562_crypto_get_rate()
1955 rate = OSC_HZ; in rk3562_crypto_get_rate()
1961 return rate; in rk3562_crypto_get_rate()
1965 ulong rate) in rk3562_crypto_set_rate() argument
1974 if (rate == 200 * MHz) in rk3562_crypto_set_rate()
1976 else if (rate == 100 * MHz) in rk3562_crypto_set_rate()
1984 if (rate == 300 * MHz) in rk3562_crypto_set_rate()
1986 else if (rate == 200 * MHz) in rk3562_crypto_set_rate()
1988 else if (rate == 100 * MHz) in rk3562_crypto_set_rate()
2014 static ulong rk3562_clk_scmi_set_rate(struct clk *clk, ulong rate) in rk3562_clk_scmi_set_rate() argument
2021 return rk3562_crypto_set_rate(priv, clk->id, rate); in rk3562_clk_scmi_set_rate()