Lines Matching refs:rate
35 .rate = _rate##U, \
46 .rate = _rate##U, \
109 struct pll_rate_table *rate = &auto_table; in pll_clk_set_by_auto() local
139 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
140 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
159 rate->refdiv = refdiv; in pll_clk_set_by_auto()
160 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
170 return rate; in pll_clk_set_by_auto()
173 static const struct pll_rate_table *get_pll_settings(unsigned long rate) in get_pll_settings() argument
179 if (rate == px30_pll_rates[i].rate) in get_pll_settings()
183 return pll_clk_set_by_auto(rate); in get_pll_settings()
186 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) in get_cpu_settings() argument
192 if (rate == px30_cpu_rates[i].rate) in get_cpu_settings()
218 const struct pll_rate_table *rate; in rkclk_set_pll() local
221 rate = get_pll_settings(drate); in rkclk_set_pll()
222 if (!rate) { in rkclk_set_pll()
228 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
229 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
232 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
233 rate->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
251 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); in rkclk_set_pll()
253 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
254 rate->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
1210 static int px30_clk_get_gpll_rate(ulong *rate) in px30_clk_get_gpll_rate() argument
1224 *rate = priv->gpll_hz; in px30_clk_get_gpll_rate()
1250 const struct cpu_rate_table *rate; in px30_armclk_set_clk() local
1253 rate = get_cpu_settings(hz); in px30_armclk_set_clk()
1254 if (!rate) { in px30_armclk_set_clk()
1271 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in px30_armclk_set_clk()
1272 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
1279 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in px30_armclk_set_clk()
1280 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
1293 ulong rate = 0; in px30_clk_get_rate() local
1303 rate = px30_clk_get_pll_rate(priv, APLL); in px30_clk_get_rate()
1306 rate = px30_clk_get_pll_rate(priv, DPLL); in px30_clk_get_rate()
1309 rate = px30_clk_get_pll_rate(priv, CPLL); in px30_clk_get_rate()
1312 rate = px30_clk_get_pll_rate(priv, NPLL); in px30_clk_get_rate()
1315 rate = px30_clk_get_pll_rate(priv, APLL); in px30_clk_get_rate()
1322 rate = px30_mmc_get_clk(priv, clk->id); in px30_clk_get_rate()
1325 rate = px30_sfc_get_clk(priv, clk->id); in px30_clk_get_rate()
1331 rate = px30_i2c_get_clk(priv, clk->id); in px30_clk_get_rate()
1334 rate = px30_i2s_get_clk(priv, clk->id); in px30_clk_get_rate()
1337 rate = px30_i2s1_mclk_get_clk(priv, clk->id); in px30_clk_get_rate()
1341 rate = px30_pwm_get_clk(priv, clk->id); in px30_clk_get_rate()
1344 rate = px30_saradc_get_clk(priv); in px30_clk_get_rate()
1347 rate = px30_tsadc_get_clk(priv); in px30_clk_get_rate()
1351 rate = px30_spi_get_clk(priv, clk->id); in px30_clk_get_rate()
1357 rate = px30_vop_get_clk(priv, clk->id); in px30_clk_get_rate()
1363 rate = px30_bus_get_clk(priv, clk->id); in px30_clk_get_rate()
1367 rate = px30_peri_get_clk(priv, clk->id); in px30_clk_get_rate()
1371 rate = px30_otp_get_clk(priv, clk->id); in px30_clk_get_rate()
1375 rate = px30_crypto_get_clk(priv, clk->id); in px30_clk_get_rate()
1381 return rate; in px30_clk_get_rate()
1384 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) in px30_clk_set_rate() argument
1394 debug("%s %ld %ld\n", __func__, clk->id, rate); in px30_clk_set_rate()
1397 ret = px30_clk_set_pll_rate(priv, NPLL, rate); in px30_clk_set_rate()
1401 px30_armclk_set_clk(priv, rate); in px30_clk_set_rate()
1402 priv->armclk_hz = rate; in px30_clk_set_rate()
1408 ret = px30_mmc_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1411 ret = px30_sfc_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1417 ret = px30_i2c_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1420 ret = px30_i2s_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1423 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1427 ret = px30_pwm_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1430 ret = px30_saradc_set_clk(priv, rate); in px30_clk_set_rate()
1433 ret = px30_tsadc_set_clk(priv, rate); in px30_clk_set_rate()
1437 ret = px30_spi_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1443 ret = px30_vop_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1448 ret = px30_bus_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1452 ret = px30_peri_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1456 ret = px30_otp_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1460 ret = px30_crypto_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1465 ret = px30_mac_set_clk(clk, rate); in px30_clk_set_rate()
1468 ret = px30_mac_set_speed_clk(clk, rate); in px30_clk_set_rate()
1496 ulong rate; in rockchip_mmc_get_phase() local
1498 rate = px30_clk_get_rate(clk); in rockchip_mmc_get_phase()
1500 if (rate < 0) in rockchip_mmc_get_phase()
1501 return rate; in rockchip_mmc_get_phase()
1514 36 * (rate / 1000000); in rockchip_mmc_get_phase()
1530 ulong rate; in rockchip_mmc_set_phase() local
1532 rate = px30_clk_get_rate(clk); in rockchip_mmc_set_phase()
1534 if (rate < 0) in rockchip_mmc_set_phase()
1535 return rate; in rockchip_mmc_set_phase()
1546 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rockchip_mmc_set_phase()
1850 ulong rate = 0; in px30_pmuclk_get_rate() local
1855 rate = px30_gpll_get_pmuclk(priv); in px30_pmuclk_get_rate()
1858 rate = px30_pclk_pmu_get_pmuclk(priv); in px30_pmuclk_get_rate()
1864 return rate; in px30_pmuclk_get_rate()
1867 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) in px30_pmuclk_set_rate() argument
1872 debug("%s %ld %ld\n", __func__, clk->id, rate); in px30_pmuclk_set_rate()
1875 ret = px30_gpll_set_pmuclk(priv, rate); in px30_pmuclk_set_rate()
1878 ret = px30_pclk_pmu_set_pmuclk(priv, rate); in px30_pmuclk_set_rate()
1990 unsigned long rate; in soc_clk_dump() local
2027 rate = clk_get_rate(&clk); in soc_clk_dump()
2030 if (rate < 0) in soc_clk_dump()
2035 rate / 1000); in soc_clk_dump()
2037 if (rate < 0) in soc_clk_dump()
2042 rate / 1000); in soc_clk_dump()