Lines Matching refs:rate
32 ulong rate; member
41 .rate = _rate##U, \
92 .rate = _rate##U, \
135 if (freq_hz == rk3368_pll_rates[i].rate) in rkclk_get_pll_config()
295 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
328 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
330 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate); in rk3368_mmc_get_clk()
331 return rate >> 1; in rk3368_mmc_get_clk()
335 ulong rate, in rk3368_mmc_find_best_rate_and_parent() argument
344 ulong rate; in rk3368_mmc_find_best_rate_and_parent() member
346 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
347 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
348 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz } in rk3368_mmc_find_best_rate_and_parent()
351 debug("%s: target rate %ld\n", __func__, rate); in rk3368_mmc_find_best_rate_and_parent()
357 ulong parent_rate = parents[i].rate; in rk3368_mmc_find_best_rate_and_parent()
358 u32 div = DIV_ROUND_UP(parent_rate, rate); in rk3368_mmc_find_best_rate_and_parent()
363 __func__, rate, parents[i].mux, parents[i].rate, div); in rk3368_mmc_find_best_rate_and_parent()
385 static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate) in rk3368_mmc_set_clk() argument
393 rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div); in rk3368_mmc_set_clk()
871 const struct rockchip_cpu_rate_table *rate; in rk3368_armclk_set_clk() local
877 rate = rockchip_get_cpu_settings(rk3368_cpu_rates, hz); in rk3368_armclk_set_clk()
878 if (!rate) { in rk3368_armclk_set_clk()
911 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3368_armclk_set_clk()
912 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3368_armclk_set_clk()
920 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in rk3368_armclk_set_clk()
921 rate->pclk_div << CORE_DBG_DIV_SHIFT); in rk3368_armclk_set_clk()
931 ulong rate = 0; in rk3368_clk_get_rate() local
941 rate = rkclk_pll_get_rate(priv->cru, clk->id - 1); in rk3368_clk_get_rate()
944 rate = rkclk_pll_get_rate(priv->cru, APLLB); in rk3368_clk_get_rate()
947 rate = rkclk_pll_get_rate(priv->cru, APLLL); in rk3368_clk_get_rate()
950 rate = rk3368_spi_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
959 rate = rk3368_bus_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
968 rate = rk3368_peri_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
973 rate = rk3368_mmc_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
977 rate = rk3368_saradc_get_clk(priv->cru); in rk3368_clk_get_rate()
982 rate = rk3368_vop_get_clk(priv->cru, clk->id); in rk3368_clk_get_rate()
985 rate = rk3368_alive_get_clk(priv); in rk3368_clk_get_rate()
988 rate = rk3368_crypto_get_rate(priv); in rk3368_clk_get_rate()
994 return rate; in rk3368_clk_get_rate()
997 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) in rk3368_clk_set_rate() argument
1010 ret = pll_para_config(rate, &pll_config, &pll_div); in rk3368_clk_set_rate()
1018 ret = rk3368_armclk_set_clk(priv, clk->id, rate); in rk3368_clk_set_rate()
1019 priv->armbclk_hz = rate; in rk3368_clk_set_rate()
1023 ret = rk3368_armclk_set_clk(priv, clk->id, rate); in rk3368_clk_set_rate()
1024 priv->armlclk_hz = rate; in rk3368_clk_set_rate()
1027 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1031 ret = rk3368_ddr_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1037 rate = rk3368_bus_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1042 rate = rk3368_peri_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1047 ret = rk3368_mmc_set_clk(clk, rate); in rk3368_clk_set_rate()
1053 ret = rk3368_gmac_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1057 ret = rk3368_saradc_set_clk(priv->cru, rate); in rk3368_clk_set_rate()
1062 ret = rk3368_vop_set_clk(priv->cru, clk->id, rate); in rk3368_clk_set_rate()
1068 ret = rk3368_crypto_set_rate(priv, rate); in rk3368_clk_set_rate()
1144 ulong rate; in rk3368_mmc_get_phase() local
1146 rate = rk3368_clk_get_rate(clk); in rk3368_mmc_get_phase()
1148 if (rate < 0) in rk3368_mmc_get_phase()
1149 return rate; in rk3368_mmc_get_phase()
1164 36 * (rate / 1000000); in rk3368_mmc_get_phase()
1180 ulong rate; in rk3368_mmc_set_phase() local
1182 rate = rk3368_clk_get_rate(clk); in rk3368_mmc_set_phase()
1184 if (rate < 0) in rk3368_mmc_set_phase()
1185 return rate; in rk3368_mmc_set_phase()
1196 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3368_mmc_set_phase()
1403 unsigned long rate; in soc_clk_dump() local
1436 rate = clk_get_rate(&clk); in soc_clk_dump()
1439 if (rate < 0) in soc_clk_dump()
1444 rate / 1000); in soc_clk_dump()
1446 if (rate < 0) in soc_clk_dump()
1451 rate / 1000); in soc_clk_dump()