Lines Matching refs:rate
25 .rate = _rate##U, \
118 ulong pll_id, ulong rate) in rk3568_pmu_pll_set_rate() argument
134 pmu_priv->pmucru, pll_id, rate); in rk3568_pmu_pll_set_rate()
226 ulong rate) in rk3568_rtc32k_set_pmuclk() argument
234 rational_best_approximation(rate, OSC_HZ, in rk3568_rtc32k_set_pmuclk()
263 ulong clk_id, ulong rate) in rk3568_i2c_set_pmuclk() argument
268 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_i2c_set_pmuclk()
307 ulong clk_id, ulong rate) in rk3568_pwm_set_pmuclk() argument
314 if (rate == OSC_HZ) { in rk3568_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pwm_set_pmuclk()
353 ulong rate) in rk3568_pmu_set_pmuclk() argument
358 src_clk_div = DIV_ROUND_UP(priv->ppll_hz, rate); in rk3568_pmu_set_pmuclk()
372 ulong rate = 0; in rk3568_pmuclk_get_rate() local
382 rate = rockchip_pll_get_rate(&rk3568_pll_clks[PPLL], in rk3568_pmuclk_get_rate()
386 rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_get_rate()
391 rate = rk3568_rtc32k_get_pmuclk(priv); in rk3568_pmuclk_get_rate()
394 rate = rk3568_i2c_get_pmuclk(priv, clk->id); in rk3568_pmuclk_get_rate()
397 rate = rk3568_pwm_get_pmuclk(priv, clk->id); in rk3568_pmuclk_get_rate()
400 rate = rk3568_pmu_get_pmuclk(priv); in rk3568_pmuclk_get_rate()
406 return rate; in rk3568_pmuclk_get_rate()
409 static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) in rk3568_pmuclk_set_rate() argument
419 debug("%s %ld %ld\n", __func__, clk->id, rate); in rk3568_pmuclk_set_rate()
423 priv->pmucru, PPLL, rate); in rk3568_pmuclk_set_rate()
429 priv->pmucru, HPLL, rate); in rk3568_pmuclk_set_rate()
435 ret = rk3568_rtc32k_set_pmuclk(priv, rate); in rk3568_pmuclk_set_rate()
438 ret = rk3568_i2c_set_pmuclk(priv, clk->id, rate); in rk3568_pmuclk_set_rate()
441 ret = rk3568_pwm_set_pmuclk(priv, clk->id, rate); in rk3568_pmuclk_set_rate()
444 ret = rk3568_pmu_set_pmuclk(priv, rate); in rk3568_pmuclk_set_rate()
556 const struct rockchip_cpu_rate_table *rate; in rk3568_armclk_set_clk() local
559 rate = rockchip_get_cpu_settings(rk3568_cpu_rates, hz); in rk3568_armclk_set_clk()
560 if (!rate) { in rk3568_armclk_set_clk()
589 rate->pclk_div << GICCLK_CORE_DIV_SHIFT | in rk3568_armclk_set_clk()
590 rate->pclk_div << ATCLK_CORE_DIV_SHIFT); in rk3568_armclk_set_clk()
594 rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT | in rk3568_armclk_set_clk()
595 rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT); in rk3568_armclk_set_clk()
598 rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT); in rk3568_armclk_set_clk()
602 rate->pclk_div << GICCLK_CORE_DIV_SHIFT | in rk3568_armclk_set_clk()
603 rate->pclk_div << ATCLK_CORE_DIV_SHIFT); in rk3568_armclk_set_clk()
607 rate->pclk_div << PCLK_CORE_PRE_DIV_SHIFT | in rk3568_armclk_set_clk()
608 rate->pclk_div << PERIPHCLK_CORE_PRE_DIV_SHIFT); in rk3568_armclk_set_clk()
611 rate->aclk_div << ACLK_CORE_NDFT_DIV_SHIFT); in rk3568_armclk_set_clk()
676 ulong clk_id, ulong rate) in rk3568_cpll_div_set_rate() argument
726 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_cpll_div_set_rate()
739 u32 con, sel, rate; in rk3568_bus_get_clk() local
746 rate = 200 * MHz; in rk3568_bus_get_clk()
748 rate = 150 * MHz; in rk3568_bus_get_clk()
750 rate = 100 * MHz; in rk3568_bus_get_clk()
752 rate = OSC_HZ; in rk3568_bus_get_clk()
759 rate = 100 * MHz; in rk3568_bus_get_clk()
761 rate = 75 * MHz; in rk3568_bus_get_clk()
763 rate = 50 * MHz; in rk3568_bus_get_clk()
765 rate = OSC_HZ; in rk3568_bus_get_clk()
771 return rate; in rk3568_bus_get_clk()
775 ulong clk_id, ulong rate) in rk3568_bus_set_clk() argument
782 if (rate == 200 * MHz) in rk3568_bus_set_clk()
784 else if (rate == 150 * MHz) in rk3568_bus_set_clk()
786 else if (rate == 100 * MHz) in rk3568_bus_set_clk()
796 if (rate == 100 * MHz) in rk3568_bus_set_clk()
798 else if (rate == 75 * MHz) in rk3568_bus_set_clk()
800 else if (rate == 50 * MHz) in rk3568_bus_set_clk()
820 u32 con, sel, rate; in rk3568_perimid_get_clk() local
827 rate = 300 * MHz; in rk3568_perimid_get_clk()
829 rate = 200 * MHz; in rk3568_perimid_get_clk()
831 rate = 100 * MHz; in rk3568_perimid_get_clk()
833 rate = OSC_HZ; in rk3568_perimid_get_clk()
839 rate = 150 * MHz; in rk3568_perimid_get_clk()
841 rate = 100 * MHz; in rk3568_perimid_get_clk()
843 rate = 75 * MHz; in rk3568_perimid_get_clk()
845 rate = OSC_HZ; in rk3568_perimid_get_clk()
851 return rate; in rk3568_perimid_get_clk()
855 ulong clk_id, ulong rate) in rk3568_perimid_set_clk() argument
862 if (rate == 300 * MHz) in rk3568_perimid_set_clk()
864 else if (rate == 200 * MHz) in rk3568_perimid_set_clk()
866 else if (rate == 100 * MHz) in rk3568_perimid_set_clk()
875 if (rate == 150 * MHz) in rk3568_perimid_set_clk()
877 else if (rate == 100 * MHz) in rk3568_perimid_set_clk()
879 else if (rate == 75 * MHz) in rk3568_perimid_set_clk()
899 u32 con, sel, rate; in rk3568_top_get_clk() local
906 rate = 500 * MHz; in rk3568_top_get_clk()
908 rate = 400 * MHz; in rk3568_top_get_clk()
910 rate = 300 * MHz; in rk3568_top_get_clk()
912 rate = OSC_HZ; in rk3568_top_get_clk()
918 rate = 400 * MHz; in rk3568_top_get_clk()
920 rate = 300 * MHz; in rk3568_top_get_clk()
922 rate = 200 * MHz; in rk3568_top_get_clk()
924 rate = OSC_HZ; in rk3568_top_get_clk()
930 rate = 150 * MHz; in rk3568_top_get_clk()
932 rate = 100 * MHz; in rk3568_top_get_clk()
934 rate = 75 * MHz; in rk3568_top_get_clk()
936 rate = OSC_HZ; in rk3568_top_get_clk()
942 rate = 100 * MHz; in rk3568_top_get_clk()
944 rate = 75 * MHz; in rk3568_top_get_clk()
946 rate = 50 * MHz; in rk3568_top_get_clk()
948 rate = OSC_HZ; in rk3568_top_get_clk()
954 return rate; in rk3568_top_get_clk()
958 ulong clk_id, ulong rate) in rk3568_top_set_clk() argument
965 if (rate == 500 * MHz) in rk3568_top_set_clk()
967 else if (rate == 400 * MHz) in rk3568_top_set_clk()
969 else if (rate == 300 * MHz) in rk3568_top_set_clk()
978 if (rate == 400 * MHz) in rk3568_top_set_clk()
980 else if (rate == 300 * MHz) in rk3568_top_set_clk()
982 else if (rate == 200 * MHz) in rk3568_top_set_clk()
991 if (rate == 150 * MHz) in rk3568_top_set_clk()
993 else if (rate == 100 * MHz) in rk3568_top_set_clk()
995 else if (rate == 75 * MHz) in rk3568_top_set_clk()
1004 if (rate == 100 * MHz) in rk3568_top_set_clk()
1006 else if (rate == 75 * MHz) in rk3568_top_set_clk()
1008 else if (rate == 50 * MHz) in rk3568_top_set_clk()
1029 ulong rate; in rk3568_i2c_get_clk() local
1040 rate = 200 * MHz; in rk3568_i2c_get_clk()
1042 rate = 100 * MHz; in rk3568_i2c_get_clk()
1044 rate = 100 * MHz; in rk3568_i2c_get_clk()
1046 rate = OSC_HZ; in rk3568_i2c_get_clk()
1052 return rate; in rk3568_i2c_get_clk()
1056 ulong rate) in rk3568_i2c_set_clk() argument
1061 if (rate == 200 * MHz) in rk3568_i2c_set_clk()
1063 else if (rate == 100 * MHz) in rk3568_i2c_set_clk()
1121 ulong clk_id, ulong rate) in rk3568_spi_set_clk() argument
1126 if (rate == 200 * MHz) in rk3568_spi_set_clk()
1128 else if (rate == 100 * MHz) in rk3568_spi_set_clk()
1195 ulong clk_id, ulong rate) in rk3568_pwm_set_clk() argument
1200 if (rate == 100 * MHz) in rk3568_pwm_set_clk()
1258 ulong clk_id, ulong rate) in rk3568_adc_set_clk() argument
1268 if (!(OSC_HZ % rate)) { in rk3568_adc_set_clk()
1269 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3568_adc_set_clk()
1279 src_clk_div = DIV_ROUND_UP(100 * MHz, rate); in rk3568_adc_set_clk()
1292 src_clk_div = DIV_ROUND_UP(prate, rate); in rk3568_adc_set_clk()
1363 ulong clk_id, ulong rate) in rk3568_crypto_set_rate() argument
1373 if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1375 else if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1377 else if (rate == 100 * MHz) in rk3568_crypto_set_rate()
1387 if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1389 else if (rate == 100 * MHz) in rk3568_crypto_set_rate()
1391 else if (rate == 75 * MHz) in rk3568_crypto_set_rate()
1399 if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1401 else if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1409 if (rate == 300 * MHz) in rk3568_crypto_set_rate()
1411 else if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1467 ulong clk_id, ulong rate) in rk3568_sdmmc_set_clk() argument
1472 switch (rate) { in rk3568_sdmmc_set_clk()
1547 static ulong rk3568_sfc_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_sfc_set_clk() argument
1552 switch (rate) { in rk3568_sfc_set_clk()
1603 static ulong rk3568_nand_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_nand_set_clk() argument
1608 switch (rate) { in rk3568_nand_set_clk()
1657 static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_emmc_set_clk() argument
1662 switch (rate) { in rk3568_emmc_set_clk()
1713 static ulong rk3568_emmc_set_bclk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_emmc_set_bclk() argument
1718 switch (rate) { in rk3568_emmc_set_bclk()
1760 static ulong rk3568_aclk_vop_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_aclk_vop_set_clk() argument
1765 if ((priv->cpll_hz % rate) == 0) { in rk3568_aclk_vop_set_clk()
1766 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_aclk_vop_set_clk()
1769 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_aclk_vop_set_clk()
1821 ulong clk_id, ulong rate) in rk3568_dclk_vop_set_clk() argument
1850 rk3568_pmu_pll_set_rate(priv, HPLL, div * rate); in rk3568_dclk_vop_set_clk()
1852 div = DIV_ROUND_UP(RK3568_VOP_PLL_LIMIT_FREQ, rate); in rk3568_dclk_vop_set_clk()
1860 priv->cru, VPLL, div * rate); in rk3568_dclk_vop_set_clk()
1878 div = DIV_ROUND_UP(pll_rate, rate); in rk3568_dclk_vop_set_clk()
1882 if (abs(rate - now) < abs(rate - best_rate)) { in rk3568_dclk_vop_set_clk()
1897 printf("do not support this vop freq %lu\n", rate); in rk3568_dclk_vop_set_clk()
1928 ulong mac_id, ulong rate) in rk3568_gmac_src_set_clk() argument
1933 switch (rate) { in rk3568_gmac_src_set_clk()
1978 ulong mac_id, ulong rate) in rk3568_gmac_out_set_clk() argument
1983 switch (rate) { in rk3568_gmac_out_set_clk()
2031 ulong mac_id, ulong rate) in rk3568_gmac_ptp_ref_set_clk() argument
2036 switch (rate) { in rk3568_gmac_ptp_ref_set_clk()
2061 ulong mac_id, ulong rate) in rk3568_gmac_tx_rx_set_clk() argument
2070 if (rate == 2500000) in rk3568_gmac_tx_rx_set_clk()
2072 else if (rate == 25000000) in rk3568_gmac_tx_rx_set_clk()
2080 if (rate == 2500000) in rk3568_gmac_tx_rx_set_clk()
2115 static ulong rk3568_ebc_set_clk(struct rk3568_clk_priv *priv, ulong rate) in rk3568_ebc_set_clk() argument
2120 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3568_ebc_set_clk()
2169 ulong clk_id, ulong rate) in rk3568_rkvdec_set_clk() argument
2183 src_clk_div = DIV_ROUND_UP(p_rate, rate); in rk3568_rkvdec_set_clk()
2202 src_clk_div = DIV_ROUND_UP(p_rate, rate); in rk3568_rkvdec_set_clk()
2280 ulong clk_id, ulong rate) in rk3568_uart_set_rate() argument
2286 if (priv->gpll_hz % rate == 0) { in rk3568_uart_set_rate()
2289 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_uart_set_rate()
2290 } else if (priv->cpll_hz % rate == 0) { in rk3568_uart_set_rate()
2293 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_uart_set_rate()
2294 } else if (rate == OSC_HZ) { in rk3568_uart_set_rate()
2302 rational_best_approximation(rate, priv->gpll_hz / div, in rk3568_uart_set_rate()
2425 ulong clk_id, ulong rate) in rk3568_i2s3_set_rate() argument
2432 if (priv->gpll_hz % rate == 0) { in rk3568_i2s3_set_rate()
2435 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_i2s3_set_rate()
2436 } else if (priv->cpll_hz % rate == 0) { in rk3568_i2s3_set_rate()
2439 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3568_i2s3_set_rate()
2440 } else if (rate == OSC_HZ / 2) { in rk3568_i2s3_set_rate()
2448 rational_best_approximation(rate, priv->gpll_hz / div, in rk3568_i2s3_set_rate()
2456 if (rate == 12000000) { in rk3568_i2s3_set_rate()
2462 rk3568_i2s3_set_rate(priv, MCLK_I2S3_2CH_TX, rate), in rk3568_i2s3_set_rate()
2470 if (rate == 12000000) { in rk3568_i2s3_set_rate()
2476 rk3568_i2s3_set_rate(priv, MCLK_I2S3_2CH_RX, rate), in rk3568_i2s3_set_rate()
2488 rk3568_i2s3_set_rate(priv, I2S3_MCLKOUT_RX, rate); in rk3568_i2s3_set_rate()
2490 rk3568_i2s3_set_rate(priv, I2S3_MCLKOUT_TX, rate); in rk3568_i2s3_set_rate()
2520 ulong rate = 0; in rk3568_clk_get_rate() local
2530 rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru, in rk3568_clk_get_rate()
2534 rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_get_rate()
2538 rate = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL], priv->cru, in rk3568_clk_get_rate()
2542 rate = rockchip_pll_get_rate(&rk3568_pll_clks[NPLL], priv->cru, in rk3568_clk_get_rate()
2546 rate = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL], priv->cru, in rk3568_clk_get_rate()
2550 rate = rockchip_pll_get_rate(&rk3568_pll_clks[DPLL], priv->cru, in rk3568_clk_get_rate()
2556 rate = rk3568_bus_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2560 rate = rk3568_perimid_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2566 rate = rk3568_top_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2573 rate = rk3568_i2c_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2579 rate = rk3568_spi_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2584 rate = rk3568_pwm_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2589 rate = rk3568_adc_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2595 rate = rk3568_sdmmc_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2598 rate = rk3568_sfc_get_clk(priv); in rk3568_clk_get_rate()
2601 rate = rk3568_nand_get_clk(priv); in rk3568_clk_get_rate()
2604 rate = rk3568_emmc_get_clk(priv); in rk3568_clk_get_rate()
2607 rate = rk3568_emmc_get_bclk(priv); in rk3568_clk_get_rate()
2610 rate = OSC_HZ; in rk3568_clk_get_rate()
2614 rate = rk3568_aclk_vop_get_clk(priv); in rk3568_clk_get_rate()
2619 rate = rk3568_dclk_vop_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2624 rate = rk3568_gmac_src_get_clk(priv, 0); in rk3568_clk_get_rate()
2627 rate = rk3568_gmac_out_get_clk(priv, 0); in rk3568_clk_get_rate()
2630 rate = rk3568_gmac_ptp_ref_get_clk(priv, 0); in rk3568_clk_get_rate()
2635 rate = rk3568_gmac_src_get_clk(priv, 1); in rk3568_clk_get_rate()
2638 rate = rk3568_gmac_out_get_clk(priv, 1); in rk3568_clk_get_rate()
2641 rate = rk3568_gmac_ptp_ref_get_clk(priv, 1); in rk3568_clk_get_rate()
2644 rate = rk3568_ebc_get_clk(priv); in rk3568_clk_get_rate()
2649 rate = rk3568_rkvdec_get_clk(priv, clk->id); in rk3568_clk_get_rate()
2652 rate = OSC_HZ; in rk3568_clk_get_rate()
2659 rate = rk3568_i2s3_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2671 rate = rk3568_uart_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2680 rate = rk3568_crypto_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2690 rate = rk3568_cpll_div_get_rate(priv, clk->id); in rk3568_clk_get_rate()
2696 return rate; in rk3568_clk_get_rate()
2699 static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) in rk3568_clk_set_rate() argument
2713 rk3568_armclk_set_clk(priv, rate); in rk3568_clk_set_rate()
2714 priv->armclk_hz = rate; in rk3568_clk_set_rate()
2718 CPLL, rate); in rk3568_clk_set_rate()
2724 GPLL, rate); in rk3568_clk_set_rate()
2730 NPLL, rate); in rk3568_clk_set_rate()
2734 VPLL, rate); in rk3568_clk_set_rate()
2742 ret = rk3568_bus_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2746 ret = rk3568_perimid_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2752 ret = rk3568_top_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2759 ret = rk3568_i2c_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2765 ret = rk3568_spi_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2770 ret = rk3568_pwm_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2775 ret = rk3568_adc_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2781 ret = rk3568_sdmmc_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2784 ret = rk3568_sfc_set_clk(priv, rate); in rk3568_clk_set_rate()
2787 ret = rk3568_nand_set_clk(priv, rate); in rk3568_clk_set_rate()
2790 ret = rk3568_emmc_set_clk(priv, rate); in rk3568_clk_set_rate()
2793 ret = rk3568_emmc_set_bclk(priv, rate); in rk3568_clk_set_rate()
2800 ret = rk3568_aclk_vop_set_clk(priv, rate); in rk3568_clk_set_rate()
2805 ret = rk3568_dclk_vop_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2810 ret = rk3568_gmac_src_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2813 ret = rk3568_gmac_out_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2816 ret = rk3568_gmac_tx_rx_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2819 ret = rk3568_gmac_ptp_ref_set_clk(priv, 0, rate); in rk3568_clk_set_rate()
2824 ret = rk3568_gmac_src_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2827 ret = rk3568_gmac_out_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2830 ret = rk3568_gmac_tx_rx_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2833 ret = rk3568_gmac_ptp_ref_set_clk(priv, 1, rate); in rk3568_clk_set_rate()
2836 ret = rk3568_ebc_set_clk(priv, rate); in rk3568_clk_set_rate()
2841 ret = rk3568_rkvdec_set_clk(priv, clk->id, rate); in rk3568_clk_set_rate()
2851 ret = rk3568_i2s3_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2863 ret = rk3568_uart_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2872 ret = rk3568_crypto_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2882 ret = rk3568_cpll_div_set_rate(priv, clk->id, rate); in rk3568_clk_set_rate()
2909 ulong rate; in rk3568_mmc_get_phase() local
2911 rate = rk3568_clk_get_rate(clk); in rk3568_mmc_get_phase()
2912 if (rate < 0) in rk3568_mmc_get_phase()
2913 return rate; in rk3568_mmc_get_phase()
2930 36 * (rate / 1000000); in rk3568_mmc_get_phase()
2946 ulong rate; in rk3568_mmc_set_phase() local
2948 rate = rk3568_clk_get_rate(clk); in rk3568_mmc_set_phase()
2949 if (rate < 0) in rk3568_mmc_set_phase()
2950 return rate; in rk3568_mmc_set_phase()
2961 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rk3568_mmc_set_phase()
3386 unsigned long rate; in soc_clk_dump() local
3423 rate = clk_get_rate(&clk); in soc_clk_dump()
3426 if (rate < 0) in soc_clk_dump()
3431 rate / 1000); in soc_clk_dump()
3433 if (rate < 0) in soc_clk_dump()
3438 rate / 1000); in soc_clk_dump()