clk: rockchip: rk3368: support get pll config by table

add some special pll configs for better clock jitter.

Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff
Signed-off-by: Elaine Zhang <zhangq

clk: rockchip: rk3368: support get pll config by table

add some special pll configs for better clock jitter.

Change-Id: I3484d36feb9f4b99a42a2ba532ae2015968d83ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3368: improve DCLK signal quality

Improved PLL output jitter can support more types of 4K TV.

Change-Id: I40a81cc276abf6ca859ad91be6785ffd15747ee5
Signed-off-by: Elaine Zhang <zhan

clk: rockchip: rk3368: improve DCLK signal quality

Improved PLL output jitter can support more types of 4K TV.

Change-Id: I40a81cc276abf6ca859ad91be6785ffd15747ee5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3368: support crypto clk get/set rate

Change-Id: I736fdda1d994ebdb59c68f8be209bae0e206be99
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3368: support pclk_wdt get rate

Change-Id: I8253532cfa6a1d492d68b0e778f625621cad5dab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3368: print arm enter and init rate

Change-Id: Ib201cf442ce7398bbe8009ce9b7de9dc1f53c587
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: mmc: add mmc set and get phase

add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chi

clk: rockchip: mmc: add mmc set and get phase

add mmc set and get phase for rk3128\rk3328\rk3368

Change-Id: Ic8d7764391165f28c54721c4af218f8623b2f3a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3368: fixup the bus and peri parent

make the bus and peri parent to GPLL.

Change-Id: I3956752c1191a6417d16fa9a9765574f38c7ab7b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3368: support more clks to set and get rate

Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.

Change-Id: I348c98ce81ce76af9c492a30480fcb49

rockchip: clk: rk3368: support more clks to set and get rate

Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.

Change-Id: I348c98ce81ce76af9c492a30480fcb495da7ed79
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: guard set_parent implementations against OF_PLATDATA

The set_parent implementations do not make sense when OF_PLATDATA is
enabled. We guard these against OF_PLATDATA and don't popula

rockchip: clk: guard set_parent implementations against OF_PLATDATA

The set_parent implementations do not make sense when OF_PLATDATA is
enabled. We guard these against OF_PLATDATA and don't populate the
set_parent-op when this is the case.

Change-Id: I37c384bf6851666550b8b3902d79b9278cff5074
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>

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clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb

clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb7
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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treewide: replace with error() with pr_err()

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h

treewide: replace with error() with pr_err()

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

# define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux. (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
(...)
// </smpl>

Change-Id: I921807c1770d36a91e692c48ab477558bb2ed0b8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 9b643e312d528f291966c1f30b0d90bf3b1d43dc)

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UPSTREAM: rockchip: clk: rk3368: Convert to livetree

Update the clock driver for the RK3368 to support a live device tree.

Change-Id: Ic74f6208fd0705c11d9a09a37c0136824fe64842
Signed-off-by: Philip

UPSTREAM: rockchip: clk: rk3368: Convert to livetree

Update the clock driver for the RK3368 to support a live device tree.

Change-Id: Ic74f6208fd0705c11d9a09a37c0136824fe64842
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 9a342f48a6c4debb1a43132c4b8ddc61c9f5d01d)

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rockchip: clk: don't reture error when not found reset driver

It's OK to continue work without reset driver.

Change-Id: I7addc19cd0a6fbbc3ebd07c1686067e5e8f4225f
Signed-off-by: Kever Yang <kever.ya

rockchip: clk: don't reture error when not found reset driver

It's OK to continue work without reset driver.

Change-Id: I7addc19cd0a6fbbc3ebd07c1686067e5e8f4225f
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.co

rockchip: clock: update sysreset driver bingding

Using priv for new sysreset driver binding.

Change-Id: I7ecc0a922086272651a6c7923afd2186c1cfeb7a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: clk: Add rk3368 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I47c

rockchip: clk: Add rk3368 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I47cc95d7e2cbf026bc34042cef4c2fe636bae674
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 615514c16dee4d43bd584ea326a5a56ebcb89c85)

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dtoc: Add support for 32 or 64-bit addresses

When using 32-bit addresses dtoc works correctly. For 64-bit addresses it
does not since it ignores the #address-cells and #size-cells properties.

Updat

dtoc: Add support for 32 or 64-bit addresses

When using 32-bit addresses dtoc works correctly. For 64-bit addresses it
does not since it ignores the #address-cells and #size-cells properties.

Update the tool to use fdt64_t as the element type for reg properties when
either the address or size is larger than one cell. Use the correct value
so that C code can obtain the information from the device tree easily.

Alos create a new type, fdt_val_t, which is defined to either fdt32_t or
fdt64_t depending on the word size of the machine. This type corresponds
to fdt_addr_t and fdt_size_t. Unfortunately we cannot just use those types
since they are defined to phys_addr_t and phys_size_t which use
'unsigned long' in the 32-bit case, rather than 'unsigned int'.

Add tests for the four combinations of address and size values (32/32,
64/64, 32/64, 64/32). Also update existing uses for rk3399 and rk3368
which now need to use the new fdt_val_t type.

Signed-off-by: Simon Glass <sjg@chromium.org>

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Reported-by: Kever Yang <kever.yang@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.

rockchip: clk: remove RATE_TO_DIV

Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: clk: rk3368: add support for configuring the SPI clocks

As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock dri

rockchip: clk: rk3368: add support for configuring the SPI clocks

As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e

rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementa

rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
- rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This

rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3368: implement MMC/SD clock reparenting

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving t

rockchip: clk: rk3368: implement MMC/SD clock reparenting

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.

This change rewrites the MMC/SD clock generation to:
* always generate a clock less-than-or-equal to the requested clock
* support reparenting among the CPLL, GPLL and OSC24M parents to
generate the highest clock that does not exceed the requested rate

In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.

This includes the changes from:
- rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implemen

rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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