| #
e583fa2a |
| 25-Aug-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: match the kernel dclk clock scheme
Change-Id: I6082edbb3147b59029812c53f03598988cb62b54
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
19191d3b |
| 04-Aug-2023 |
Jonas Karlman <jonas@kwiboo.se> |
UPSTREAM: clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in
UPSTREAM: clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.
The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.
Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.
Change-Id: Iaf6ba930cc29ac3233cf5d046002f71a6879eb78
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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| #
98d806de |
| 04-Aug-2023 |
Jonas Karlman <jonas@kwiboo.se> |
UPSTREAM: clk: rockchip: rk3568: Include UART clocks in SPL
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough logleve
UPSTREAM: clk: rockchip: rk3568: Include UART clocks in SPL
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.
ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Fix this by including support for UART clocks in SPL.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Change-Id: I788dbf470d1f8eff75e6db8073f05207579dd9e1
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
0de0139e |
| 04-Aug-2023 |
Jonas Karlman <jonas@kwiboo.se> |
UPSTREAM: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
UPSTREAM: clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Change-Id: Icc9fda366d0428b2b425a74c7ea2c5a5c1489d2f
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
ea2fe5aa |
| 22-Jul-2023 |
Jonas Karlman <jonas@kwiboo.se> |
UPSTREAM: rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support
Add dummy support for the CLK_PCIEPHY2_REF clock.
Change-Id: Ic1593bbfb829b67d4f703b3b821a6cc3b0744bd2
Signed-off-by: Jonas Karlman
UPSTREAM: rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF support
Add dummy support for the CLK_PCIEPHY2_REF clock.
Change-Id: Ic1593bbfb829b67d4f703b3b821a6cc3b0744bd2
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
14d9ba56 |
| 16-Jun-2023 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support dclk_vop select more parent clks
Change-Id: Ib823620ff7940f8d62e78010817ca9b5f06995dd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
988eb0b8 |
| 19-Apr-2023 |
Damon Ding <damon.ding@rock-chips.com> |
clk: rockchip: rk3568: fix clk selection in rk3568_pwm_get_clk()
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I21e5622d8253817820a091c9bf06ec3f2b76de4a
|
| #
c6f7c1a3 |
| 18-Aug-2022 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: Add rk3528 support
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I0683071e9bdde1cb5aa4c3df40750f33a3faa85b
|
| #
75c04b2a |
| 26-Sep-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support emmc bclk and tclk
Change-Id: I149021d6492d4a72662b116dc78c93be8f40c0fb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
fae8dbc4 |
| 22-Sep-2021 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk3568: add freq (26 * MHz) for mmc device
The mmc device set the high speed mode freq to (26 * MHz),
like sd card.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I38
clk: rockchip: rk3568: add freq (26 * MHz) for mmc device
The mmc device set the high speed mode freq to (26 * MHz),
like sd card.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I38242e2d2cf18544464f0010b550b59e54b9d0bd
show more ...
|
| #
26663c2d |
| 23-Jul-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: add i2s3 clk
Change-Id: If20fe16260d2b584d4216d1dbabffcb25478fb1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
1e414535 |
| 30-Jun-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: fix up the sfc clk rate unit error
Change-Id: Iae8571a7c2d185883ea6bf263813b94c101560aa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
563d12f2 |
| 09-Apr-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: add uart clk
Change-Id: I92a097e216e9cbb254c5bae5a25bc52f0c53cd38
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
0a741659 |
| 02-Mar-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support aclk_vop setting 500M
add cpll as aclk_vop parent.
Change-Id: I4dd4bb846191c6f44f430ddbeea92017c1276d93
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
d504dfb2 |
| 04-Jan-2021 |
Shawn Lin <shawn.lin@rock-chips.com> |
clk: rockchip: rk3568: Ungate PCIe30phy refclk_m and refclk_n
Change-Id: I718f280cd78235131f3f3ef76e17e498a6e4db8e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
|
| #
6c0e8ad8 |
| 25-Dec-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support wdt clk set/get rate
Change-Id: I04b868618f0590b44cea8c00041b9fb676e55919
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
aa003068 |
| 24-Dec-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: fix up the return value for rk3568_clk_set_rate()
Change-Id: If472e1b954624ff5205e3064d484de3533cde949
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
98637248 |
| 22-Dec-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk3568: fix print error log
The log is "Fail to set the ACLK_BUS clock"
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ie22e5139e1446ae751d1e64729c7a0b4cdbac69e
|
| #
0a04fb50 |
| 09-Dec-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support rkvdec clk setting
Change-Id: Ic63b3c8ecbefcdf551d646ebb40521e6b521610b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
77e56285 |
| 03-Dec-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk3568: support set sdmmc0 clock
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ic7bdfce9a9551649e053f58b6d9219e73e6afed5
|
| #
f6d27794 |
| 01-Dec-2020 |
zhangqing <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support more clk setting
support cpll_xxx settings.
Change-Id: I2735f6abe0fb02828b7ace76b58a60757199cab8
Signed-off-by: zhangqing <zhangqing@rock-chips.com>
|
| #
65bd598f |
| 17-Nov-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl
Since the mcu uses the ACLK_BUS clock and 150MHz is need as
default clock rate.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-I
clk: rockchip: rk3568: set the ACLK_BUS to 150MHz in spl
Since the mcu uses the ACLK_BUS clock and 150MHz is need as
default clock rate.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I60c4603fa0c0b45667c6583992ea461fed18fcf5
show more ...
|
| #
fdd74c32 |
| 12-Nov-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support ebc clk setting/getting rate
Change-Id: Iecac8e56b2b5615b54c8969767053b6282fe6fb8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
802c460a |
| 16-Nov-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: support ppll setting 200M
Change-Id: If5d4d1994956a8e18f3208a22daee6efca80950b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
801ca42b |
| 10-Nov-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3568: fix up the vpll register address
Fix up the error description of TRM.
Change-Id: Ie95482efea4e78505d361b5377ff4a23826d69e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.c
clk: rockchip: rk3568: fix up the vpll register address
Fix up the error description of TRM.
Change-Id: Ie95482efea4e78505d361b5377ff4a23826d69e3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|