76 	.rate	= _rate##U,					\
121 	const struct rockchip_cpu_rate_table *rate;  in rk3328_armclk_set_clk()  local
124 	rate = rockchip_get_cpu_settings(rk3328_cpu_rates, hz);  in rk3328_armclk_set_clk()
125 	if (!rate) {  in rk3328_armclk_set_clk()
147 			     rate->aclk_div << CORE_ACLK_DIV_SHIFT |  in rk3328_armclk_set_clk()
148 			     rate->pclk_div << CORE_DBG_DIV_SHIFT);  in rk3328_armclk_set_clk()
152 			     rate->aclk_div << CORE_ACLK_DIV_SHIFT |  in rk3328_armclk_set_clk()
153 			     rate->pclk_div << CORE_DBG_DIV_SHIFT);  in rk3328_armclk_set_clk()
243 static ulong rk3328_gmac2io_set_clk(struct rk3328_clk_priv *priv, ulong rate)  in rk3328_gmac2io_set_clk()  argument
258 		ret = rate;  in rk3328_gmac2io_set_clk()
269 		div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rk3328_gmac2io_set_clk()
282 static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate)  in rk3328_gmac2phy_src_set_clk()  argument
293 	div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rk3328_gmac2phy_src_set_clk()
303 static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate)  in rk3328_gmac2phy_set_clk()  argument
310 		return rate;  in rk3328_gmac2phy_set_clk()
312 		return rk3328_gmac2phy_src_set_clk(cru, rate);  in rk3328_gmac2phy_set_clk()
784 	ulong rate = 0;  in rk3328_clk_get_rate()  local
805 		rate = rockchip_pll_get_rate(&rk3328_pll_clks[clk->id - 1],  in rk3328_clk_get_rate()
809 		rate = rockchip_pll_get_rate(&rk3328_pll_clks[NPLL],  in rk3328_clk_get_rate()
815 		rate = rk3328_bus_get_clk(priv, clk->id);  in rk3328_clk_get_rate()
820 		rate = rk3328_peri_get_clk(priv, clk->id);  in rk3328_clk_get_rate()
827 		rate = rk3328_mmc_get_clk(priv, clk->id);  in rk3328_clk_get_rate()
830 		rate = rk3328_spi_get_clk(priv);  in rk3328_clk_get_rate()
837 		rate = rk3328_i2c_get_clk(priv, clk->id);  in rk3328_clk_get_rate()
840 		rate = rk3328_pwm_get_clk(priv);  in rk3328_clk_get_rate()
843 		rate = rk3328_saradc_get_clk(priv);  in rk3328_clk_get_rate()
846 		rate = rk3328_tsadc_get_clk(priv);  in rk3328_clk_get_rate()
854 		rate = rk3328_vop_get_clk(priv, clk->id);  in rk3328_clk_get_rate()
857 		rate = rk3328_crypto_get_clk(priv, clk->id);  in rk3328_clk_get_rate()
864 	return rate;  in rk3328_clk_get_rate()
867 static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)  in rk3328_clk_set_rate()  argument
877 					    priv->cru, clk->id - 1, rate);  in rk3328_clk_set_rate()
881 					    priv->cru, CPLL, rate);  in rk3328_clk_set_rate()
882 		priv->cpll_hz = rate;  in rk3328_clk_set_rate()
886 					    priv->cru, GPLL, rate);  in rk3328_clk_set_rate()
887 		priv->gpll_hz = rate;  in rk3328_clk_set_rate()
891 			ret = rk3328_armclk_set_clk(priv, rate);  in rk3328_clk_set_rate()
892 		priv->armclk_hz = rate;  in rk3328_clk_set_rate()
897 		rate = rk3328_bus_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
902 		rate = rk3328_peri_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
908 		ret = rk3328_mmc_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
911 		ret = rk3328_spi_set_clk(priv, rate);  in rk3328_clk_set_rate()
918 		ret = rk3328_i2c_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
921 		ret = rk3328_gmac2io_set_clk(priv, rate);  in rk3328_clk_set_rate()
924 		ret = rk3328_gmac2phy_set_clk(priv->cru, rate);  in rk3328_clk_set_rate()
927 		ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate);  in rk3328_clk_set_rate()
930 		ret = rk3328_pwm_set_clk(priv, rate);  in rk3328_clk_set_rate()
933 		ret = rk3328_saradc_set_clk(priv, rate);  in rk3328_clk_set_rate()
936 		ret = rk3328_tsadc_set_clk(priv, rate);  in rk3328_clk_set_rate()
945 		rate = rk3328_vop_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
948 		rate = rk3328_crypto_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
1161 	ulong rate;  in rk3328_mmc_get_phase()  local
1163 	rate = rk3328_clk_get_rate(clk);  in rk3328_mmc_get_phase()
1165 	if (rate < 0)  in rk3328_mmc_get_phase()
1166 		return rate;  in rk3328_mmc_get_phase()
1181 					36 * (rate / 1000000);  in rk3328_mmc_get_phase()
1197 	ulong rate;  in rk3328_mmc_set_phase()  local
1199 	rate = rk3328_clk_get_rate(clk);  in rk3328_mmc_set_phase()
1201 	if (rate < 0)  in rk3328_mmc_set_phase()
1202 		return rate;  in rk3328_mmc_set_phase()
1213 	delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *  in rk3328_mmc_set_phase()
1421 	unsigned long rate;  in soc_clk_dump()  local
1448 			rate = clk_get_rate(&clk);  in soc_clk_dump()
1451 				if (rate < 0)  in soc_clk_dump()
1456 					       rate / 1000);  in soc_clk_dump()
1458 				if (rate < 0)  in soc_clk_dump()
1463 					       rate / 1000);  in soc_clk_dump()