52 	.rate	= _rate##U,					\
94 	const struct rockchip_cpu_rate_table *rate;  in rk3128_armclk_set_clk()  local
97 	rate = rockchip_get_cpu_settings(rk3128_cpu_rates, hz);  in rk3128_armclk_set_clk()
98 	if (!rate) {  in rk3128_armclk_set_clk()
120 			     rate->aclk_div << CORE_ACLK_DIV_SHIFT |  in rk3128_armclk_set_clk()
121 			     rate->pclk_div << CORE_DBG_DIV_SHIFT);  in rk3128_armclk_set_clk()
125 			     rate->aclk_div << CORE_ACLK_DIV_SHIFT |  in rk3128_armclk_set_clk()
126 			     rate->pclk_div << CORE_DBG_DIV_SHIFT);  in rk3128_armclk_set_clk()
532 	ulong rate = 0;  in rk3128_clk_get_rate()  local
539 		rate =  rockchip_pll_get_rate(&rk3128_pll_clks[clk->id - 1],  in rk3128_clk_get_rate()
543 		rate = rockchip_pll_get_rate(&rk3128_pll_clks[APLL],  in rk3128_clk_get_rate()
552 		rate = rockchip_mmc_get_clk(priv, clk->id);  in rk3128_clk_get_rate()
563 		rate = rk3128_peri_get_clk(priv, clk->id);  in rk3128_clk_get_rate()
568 		rate = rk3128_bus_get_clk(priv, clk->id);  in rk3128_clk_get_rate()
571 		rate = rk3128_spi_get_clk(priv);  in rk3128_clk_get_rate()
575 		rate = rk3128_saradc_get_clk(priv);  in rk3128_clk_get_rate()
581 		rate = rk3128_vop_get_rate(priv, clk->id);  in rk3128_clk_get_rate()
584 		rate = rk3128_crypto_get_rate(priv);  in rk3128_clk_get_rate()
590 	return rate;  in rk3128_clk_get_rate()
593 static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)  in rk3128_clk_set_rate()  argument
603 					    priv->cru, clk->id - 1, rate);  in rk3128_clk_set_rate()
606 					    priv->cru, GPLL, rate);  in rk3128_clk_set_rate()
607 		priv->gpll_hz = rate;  in rk3128_clk_set_rate()
611 			ret = rk3128_armclk_set_clk(priv, rate);  in rk3128_clk_set_rate()
612 		priv->armclk_hz = rate;  in rk3128_clk_set_rate()
623 		ret = rockchip_mmc_set_clk(priv, clk->id, rate);  in rk3128_clk_set_rate()
633 		ret = rk3128_peri_set_clk(priv, clk->id, rate);  in rk3128_clk_set_rate()
638 		ret = rk3128_bus_set_clk(priv, clk->id, rate);  in rk3128_clk_set_rate()
641 		ret = rk3128_spi_set_clk(priv, rate);  in rk3128_clk_set_rate()
645 		ret = rk3128_saradc_set_clk(priv, rate);  in rk3128_clk_set_rate()
651 		ret = rk3128_vop_set_clk(priv, clk->id, rate);  in rk3128_clk_set_rate()
654 		ret = rk3128_crypto_set_rate(priv, rate);  in rk3128_clk_set_rate()
681 	ulong rate;  in rk3128_mmc_get_phase()  local
683 	rate = rk3128_clk_get_rate(clk);  in rk3128_mmc_get_phase()
685 	if (rate < 0)  in rk3128_mmc_get_phase()
686 		return rate;  in rk3128_mmc_get_phase()
701 					36 * (rate / 1000000);  in rk3128_mmc_get_phase()
717 	ulong rate;  in rk3128_mmc_set_phase()  local
719 	rate = rk3128_clk_get_rate(clk);  in rk3128_mmc_set_phase()
721 	if (rate < 0)  in rk3128_mmc_set_phase()
722 		return rate;  in rk3128_mmc_set_phase()
733 	delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *  in rk3128_mmc_set_phase()
926 	unsigned long rate;  in soc_clk_dump()  local
953 			rate = clk_get_rate(&clk);  in soc_clk_dump()
956 				if (rate < 0)  in soc_clk_dump()
961 					       rate / 1000);  in soc_clk_dump()
963 				if (rate < 0)  in soc_clk_dump()
968 					       rate / 1000);  in soc_clk_dump()