clk: rockchip: Extend pll timeout value

Fix the error:
rk3036_pll_set_rate: wait pll lock timeout! pll_id=2

Change-Id: I66b1a89b67c2601bb02b7ee84ecf509fd7acd8ab
Signed-off-by: Jon Lin <jon.lin@roc

clk: rockchip: Extend pll timeout value

Fix the error:
rk3036_pll_set_rate: wait pll lock timeout! pll_id=2

Change-Id: I66b1a89b67c2601bb02b7ee84ecf509fd7acd8ab
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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clk: rockchip: fix the 32-bit may overflow

Fixes: e583fa2ab810 ("clk: rockchip: match the kernel dclk clock scheme")
Change-Id: Ie48647f45eb45147156d6c5110ab4e4d85e5a7ab
Signed-off-by: Elaine Zhang

clk: rockchip: fix the 32-bit may overflow

Fixes: e583fa2ab810 ("clk: rockchip: match the kernel dclk clock scheme")
Change-Id: Ie48647f45eb45147156d6c5110ab4e4d85e5a7ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: match the kernel dclk clock scheme

Change-Id: I6082edbb3147b59029812c53f03598988cb62b54
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3588: fix up the frac pll calculation

rk3588 frac pll:
FFVCO = ((m + k / 65536) * FFIN) / p
FFOUT = ((m + k / 65536) * FFIN) / (p * 2s)
k is the original code, but the K[15:0] is co

clk: rockchip: rk3588: fix up the frac pll calculation

rk3588 frac pll:
FFVCO = ((m + k / 65536) * FFIN) / p
FFOUT = ((m + k / 65536) * FFIN) / (p * 2s)
k is the original code, but the K[15:0] is complement code
(6'b1000_0000_0000_0000 <= K[15:0] <= 16'b0111_1111_1111_1111),
need to be converted.

Change-Id: I81ee91c43cb49bbc985f7006a6a29f6b8c3110ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: Add rk3528 support

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I0683071e9bdde1cb5aa4c3df40750f33a3faa85b

clk: rockchip: rk3588: optimized Pll automatic calculation

Change-Id: I920fbe21caa5fe8e198985564b474f85028e16f6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk/rockchip: pll: Use UL for FREQ definition to avoid integer overflow

Fixes: 7f3ced6dec69 ("rockchip: clk: pll: add pll_rk3588 type for RK3588 Soc")
Change-Id: I38526a0f3426603968f9f400d25d814d241

clk/rockchip: pll: Use UL for FREQ definition to avoid integer overflow

Fixes: 7f3ced6dec69 ("rockchip: clk: pll: add pll_rk3588 type for RK3588 Soc")
Change-Id: I38526a0f3426603968f9f400d25d814d241a61bc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

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clk: rockchip: pll: rk3588: set core div after pll setting

Change-Id: Ied1fcf8637080ad6ab3d1bc28e9f21f6ad1c23dc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: pll: enable clk_bisr after cpll setting

Fixes: 09fc4831933d ("clk: rockchip: pll: fix cpll setting error")

Change-Id: Idaebec5a07bffaf4902fe9cd0fdeb28a05e76e6b
Signed-off-by: Elaine

clk: rockchip: pll: enable clk_bisr after cpll setting

Fixes: 09fc4831933d ("clk: rockchip: pll: fix cpll setting error")

Change-Id: Idaebec5a07bffaf4902fe9cd0fdeb28a05e76e6b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: pll: fix cpll setting error

Change-Id: I1091f037b249a0e803ea1d6dd816a66258e7cd8e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: pll: add lock timeout

It's more friendly for FPGA board.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8b6eb63ddf2b5c8742941e4e62444acba88feb31

rockchip: clk: pll: add pll_rk3588 type for RK3588 Soc

Change-Id: I8b38afb9f51847543da4df6305996dc5845d7876
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: add debug info for waiting pll

On FPGA, PLL is fake and can't give a lock state which causes
dead waiting, so that adding a debug message to easily notice
this situation.

Change-Id:

clk: rockchip: add debug info for waiting pll

On FPGA, PLL is fake and can't give a lock state which causes
dead waiting, so that adding a debug message to easily notice
this situation.

Change-Id: Ic7dccedb3d7e5c7588da85bb4c4552b924f60e43
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: clk: pll: Fix pll rate overflow calculation on 32-bit

Change-Id: Ide0a10a19218443fa016ee91b5a18cfbf3e0948d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: pll: add common pll setting funcs

Change-Id: I99887338a4f84aead905938eee066b460c4c1b9f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>