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Searched refs:con (Results 1 – 25 of 47) sorted by relevance

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/rk3399_rockchip-uboot/test/dm/
H A Dvideo.c106 struct udevice *dev, *con; in dm_test_video_text() local
116 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); in dm_test_video_text()
117 vidconsole_putc_xy(con, 0, 0, 'a'); in dm_test_video_text()
120 vidconsole_putc_xy(con, 0, 0, ' '); in dm_test_video_text()
124 vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); in dm_test_video_text()
127 vidconsole_set_row(con, 0, WHITE); in dm_test_video_text()
131 vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); in dm_test_video_text()
141 struct udevice *dev, *con; in dm_test_video_chars() local
147 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); in dm_test_video_chars()
149 vidconsole_put_char(con, *s); in dm_test_video_chars()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3576.c172 u32 con, sel, div, rate; in rk3576_bus_get_clk() local
176 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
177 sel = (con & ACLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
179 div = (con & ACLK_BUS_ROOT_DIV_MASK) >> in rk3576_bus_get_clk()
187 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
188 sel = (con & HCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
200 con = readl(&cru->clksel_con[55]); in rk3576_bus_get_clk()
201 sel = (con & PCLK_BUS_ROOT_SEL_MASK) >> in rk3576_bus_get_clk()
278 u32 con, sel, div, rate, prate; in rk3576_top_get_clk() local
282 con = readl(&cru->clksel_con[9]); in rk3576_top_get_clk()
[all …]
H A Dclk_rv1126b.c78 u32 con, sel, rate; in rv1126b_peri_get_clk() local
82 con = readl(&cru->clksel_con[47]); in rv1126b_peri_get_clk()
83 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1126b_peri_get_clk()
90 con = readl(&cru->clksel_con[47]); in rv1126b_peri_get_clk()
91 sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT; in rv1126b_peri_get_clk()
98 con = readl(&cru->clksel_con[44]); in rv1126b_peri_get_clk()
99 sel = (con & ACLK_TOP_SEL_MASK) >> ACLK_TOP_SEL_SHIFT; in rv1126b_peri_get_clk()
113 con = readl(&cru->clksel_con[44]); in rv1126b_peri_get_clk()
114 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rv1126b_peri_get_clk()
123 con = readl(&cru->clksel_con[44]); in rv1126b_peri_get_clk()
[all …]
H A Dclk_rk3506.c188 u32 sel, con, div; in rk3506_armclk_get_rate() local
191 con = readl(&cru->clksel_con[15]); in rk3506_armclk_get_rate()
192 sel = (con & CLK_CORE_SRC_SEL_MASK) >> CLK_CORE_SRC_SEL_SHIFT; in rk3506_armclk_get_rate()
193 div = (con & CLK_CORE_SRC_DIV_MASK) >> CLK_CORE_SRC_DIV_SHIFT; in rk3506_armclk_get_rate()
212 u32 con, sel, div, old_div; in rk3506_armclk_set_rate() local
246 con = readl(&cru->clksel_con[15]); in rk3506_armclk_set_rate()
247 old_div = (con & CLK_CORE_SRC_DIV_MASK) >> CLK_CORE_SRC_DIV_SHIFT; in rk3506_armclk_set_rate()
273 u32 con, div; in rk3506_pll_div_get_rate() local
278 con = readl(&cru->clksel_con[0]); in rk3506_pll_div_get_rate()
279 div = (con & CLK_GPLL_DIV_MASK) >> CLK_GPLL_DIV_SHIFT; in rk3506_pll_div_get_rate()
[all …]
H A Dclk_rv1103b.c65 u32 con, sel, div, rate, prate; in rv1103b_peri_get_clk() local
69 con = readl(&cru->clksel_con[31]); in rv1103b_peri_get_clk()
70 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1103b_peri_get_clk()
79 con = readl(&cru->clksel_con[31]); in rv1103b_peri_get_clk()
80 sel = (con & LSCLK_PERI_SEL_MASK) >> LSCLK_PERI_SEL_SHIFT; in rv1103b_peri_get_clk()
87 con = readl(&cru->peri_clksel_con[0]); in rv1103b_peri_get_clk()
88 div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT; in rv1103b_peri_get_clk()
97 con = readl(&cru->pmu_clksel_con[2]); in rv1103b_peri_get_clk()
98 sel = (con & LSCLK_PMU_SEL_MASK) >> LSCLK_PMU_SEL_SHIFT; in rv1103b_peri_get_clk()
99 div = (con & LSCLK_PMU_DIV_MASK) >> LSCLK_PMU_DIV_SHIFT; in rv1103b_peri_get_clk()
[all …]
H A Dclk_rk3588.c154 u32 con, sel, rate; in rk3588_center_get_clk() local
158 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
159 sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
171 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
172 sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
184 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
185 sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
197 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
198 sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
286 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
[all …]
H A Dclk_rk3036.c205 uint32_t con; in rkclk_pll_get_rate() local
219 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
223 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
229 con = readl(&pll->con0); in rkclk_pll_get_rate()
230 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
231 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
232 con = readl(&pll->con1); in rkclk_pll_get_rate()
233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
234 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
247 u32 con; in rockchip_mmc_get_clk() local
[all …]
H A Dclk_rv1126.c217 u32 div, con; in rv1126_i2c_get_pmuclk() local
221 con = readl(&pmucru->pmu_clksel_con[2]); in rv1126_i2c_get_pmuclk()
222 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; in rv1126_i2c_get_pmuclk()
225 con = readl(&pmucru->pmu_clksel_con[3]); in rv1126_i2c_get_pmuclk()
226 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; in rv1126_i2c_get_pmuclk()
264 u32 div, sel, con; in rv1126_pwm_get_pmuclk() local
268 con = readl(&pmucru->pmu_clksel_con[6]); in rv1126_pwm_get_pmuclk()
269 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1126_pwm_get_pmuclk()
270 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rv1126_pwm_get_pmuclk()
275 con = readl(&pmucru->pmu_clksel_con[6]); in rv1126_pwm_get_pmuclk()
[all …]
H A Dclk_rv1106.c79 u32 con, sel, rate; in rv1106_peri_get_clk() local
83 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
84 sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT; in rv1106_peri_get_clk()
95 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
96 sel = (con & HCLK_PERI_SEL_MASK) >> HCLK_PERI_SEL_SHIFT; in rv1106_peri_get_clk()
107 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
108 sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT; in rv1106_peri_get_clk()
117 con = readl(&cru->peri_clksel_con[9]); in rv1106_peri_get_clk()
118 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rv1106_peri_get_clk()
129 con = readl(&cru->clksel_con[24]); in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3568.c248 u32 div, con; in rk3568_i2c_get_pmuclk() local
252 con = readl(&pmucru->pmu_clksel_con[3]); in rk3568_i2c_get_pmuclk()
253 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; in rk3568_i2c_get_pmuclk()
287 u32 div, sel, con, parent; in rk3568_pwm_get_pmuclk() local
291 con = readl(&pmucru->pmu_clksel_con[6]); in rk3568_pwm_get_pmuclk()
292 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rk3568_pwm_get_pmuclk()
293 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rk3568_pwm_get_pmuclk()
339 u32 div, con, sel, parent; in rk3568_pmu_get_pmuclk() local
341 con = readl(&pmucru->pmu_clksel_con[2]); in rk3568_pmu_get_pmuclk()
342 sel = (con & PCLK_PDPMU_SEL_MASK) >> PCLK_PDPMU_SEL_SHIFT; in rk3568_pmu_get_pmuclk()
[all …]
H A Dclk_rk1808.c98 u32 div, con; in rk1808_i2c_get_clk() local
102 con = readl(&cru->pmu_clksel_con[7]); in rk1808_i2c_get_clk()
103 div = (con & CLK_I2C0_DIV_CON_MASK) >> CLK_I2C0_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
106 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
107 div = (con & CLK_I2C1_DIV_CON_MASK) >> CLK_I2C1_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
110 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
111 div = (con & CLK_I2C2_DIV_CON_MASK) >> CLK_I2C2_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
114 con = readl(&cru->clksel_con[60]); in rk1808_i2c_get_clk()
115 div = (con & CLK_I2C3_DIV_CON_MASK) >> CLK_I2C3_DIV_CON_SHIFT; in rk1808_i2c_get_clk()
118 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
[all …]
H A Dclk_rk3562.c205 u32 sel, con, div; in rk3562_bus_get_rate() local
210 con = readl(&cru->clksel_con[40]); in rk3562_bus_get_rate()
211 sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT; in rk3562_bus_get_rate()
212 div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
215 con = readl(&cru->clksel_con[40]); in rk3562_bus_get_rate()
216 sel = (con & HCLK_BUS_SEL_MASK) >> HCLK_BUS_SEL_SHIFT; in rk3562_bus_get_rate()
217 div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
220 con = readl(&cru->clksel_con[41]); in rk3562_bus_get_rate()
221 sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT; in rk3562_bus_get_rate()
222 div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT; in rk3562_bus_get_rate()
[all …]
H A Dclk_rk3308.c200 u32 div, con, con_id; in rk3308_i2c_get_clk() local
220 con = readl(&cru->clksel_con[con_id]); in rk3308_i2c_get_clk()
221 div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3308_i2c_get_clk()
264 u32 con = readl(&cru->clksel_con[43]); in rk3308_mac_set_clk() local
268 if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL0) in rk3308_mac_set_clk()
271 else if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL1) in rk3308_mac_set_clk()
310 u32 div, con, con_id; in rk3308_mmc_get_clk() local
326 con = readl(&cru->clksel_con[con_id]); in rk3308_mmc_get_clk()
327 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rk3308_mmc_get_clk()
329 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT in rk3308_mmc_get_clk()
[all …]
H A Dclk_px30.c273 u32 con, shift, mask; in rkclk_pll_get_rate() local
275 con = readl(mode); in rkclk_pll_get_rate()
279 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
284 con = readl(&pll->con0); in rkclk_pll_get_rate()
285 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
286 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
287 con = readl(&pll->con1); in rkclk_pll_get_rate()
288 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
289 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
300 u32 div, con; in px30_i2c_get_clk() local
[all …]
H A Dclk_rk322x.c146 u32 con; in rk322x_mmc_get_clk() local
152 con = readl(&cru->cru_clksel_con[11]); in rk322x_mmc_get_clk()
153 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rk322x_mmc_get_clk()
154 con = readl(&cru->cru_clksel_con[12]); in rk322x_mmc_get_clk()
155 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rk322x_mmc_get_clk()
160 con = readl(&cru->cru_clksel_con[11]); in rk322x_mmc_get_clk()
161 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; in rk322x_mmc_get_clk()
162 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; in rk322x_mmc_get_clk()
166 con = readl(&cru->cru_clksel_con[11]); in rk322x_mmc_get_clk()
167 mux = (con & SDIO_PLL_MASK) >> SDIO_PLL_SHIFT; in rk322x_mmc_get_clk()
[all …]
H A Dclk_rk3328.c170 u32 div, con; in rk3328_i2c_get_clk() local
174 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
175 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
178 con = readl(&cru->clksel_con[34]); in rk3328_i2c_get_clk()
179 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
182 con = readl(&cru->clksel_con[35]); in rk3328_i2c_get_clk()
183 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
186 con = readl(&cru->clksel_con[35]); in rk3328_i2c_get_clk()
187 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in rk3328_i2c_get_clk()
260 u32 con = readl(&cru->clksel_con[27]); in rk3328_gmac2io_set_clk() local
[all …]
H A Dclk_rk3399.c345 u32 con; in rkclk_pll_get_rate() local
347 con = readl(&pll_con[3]); in rkclk_pll_get_rate()
348 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { in rkclk_pll_get_rate()
353 con = readl(&pll_con[0]); in rkclk_pll_get_rate()
354 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
355 con = readl(&pll_con[1]); in rkclk_pll_get_rate()
356 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
358 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
572 #define I2C_CLK_DIV_VALUE(con, bus) \ argument
[all …]
H A Dclk_rk3528.c327 u32 sel, div, mask, shift, con; in rk3528_cgpll_matrix_get_rate() local
335 con = 0; in rk3528_cgpll_matrix_get_rate()
342 con = 0; in rk3528_cgpll_matrix_get_rate()
349 con = 1; in rk3528_cgpll_matrix_get_rate()
355 con = 1; in rk3528_cgpll_matrix_get_rate()
361 con = 1; in rk3528_cgpll_matrix_get_rate()
369 con = 2; in rk3528_cgpll_matrix_get_rate()
375 con = 2; in rk3528_cgpll_matrix_get_rate()
382 con = 2; in rk3528_cgpll_matrix_get_rate()
388 con = 3; in rk3528_cgpll_matrix_get_rate()
[all …]
H A Dclk_rk3128.c145 u32 con; in rockchip_mmc_get_clk() local
151 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
152 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
153 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
158 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
159 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; in rockchip_mmc_get_clk()
160 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; in rockchip_mmc_get_clk()
165 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
166 mux = (con & SDIO_PLL_MASK) >> SDIO_PLL_SHIFT; in rockchip_mmc_get_clk()
167 div = (con & SDIO_DIV_MASK) >> SDIO_DIV_SHIFT; in rockchip_mmc_get_clk()
[all …]
H A Dclk_rk3288.c273 u32 con; in rkclk_pll_get_rate() local
282 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
284 switch ((con >> shift) & CRU_MODE_MASK) { in rkclk_pll_get_rate()
289 con = readl(&pll->con0); in rkclk_pll_get_rate()
290 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; in rkclk_pll_get_rate()
291 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; in rkclk_pll_get_rate()
292 con = readl(&pll->con1); in rkclk_pll_get_rate()
293 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; in rkclk_pll_get_rate()
448 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk() local
452 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == in rockchip_mac_set_clk()
[all …]
H A Dclk_rk3066.c251 uint32_t con; in rkclk_pll_get_rate() local
260 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
262 switch ((con >> shift) & APLL_MODE_MASK >> APLL_MODE_SHIFT) { in rkclk_pll_get_rate()
267 con = readl(&pll->con0); in rkclk_pll_get_rate()
268 no = ((con >> CLKOD_SHIFT) & (CLKOD_MASK >> CLKOD_SHIFT)) + 1; in rkclk_pll_get_rate()
269 nr = ((con >> CLKR_SHIFT) & (CLKR_MASK >> CLKR_SHIFT)) + 1; in rkclk_pll_get_rate()
270 con = readl(&pll->con1); in rkclk_pll_get_rate()
271 nf = ((con >> CLKF_SHIFT) & (CLKF_MASK >> CLKF_SHIFT)) + 1; in rkclk_pll_get_rate()
284 u32 con; in rockchip_mmc_get_clk() local
288 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
[all …]
H A Dclk_rk3188.c249 uint32_t con; in rkclk_pll_get_rate() local
258 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
260 switch ((con >> shift) & APLL_MODE_MASK) { in rkclk_pll_get_rate()
265 con = readl(&pll->con0); in rkclk_pll_get_rate()
266 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; in rkclk_pll_get_rate()
267 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; in rkclk_pll_get_rate()
268 con = readl(&pll->con1); in rkclk_pll_get_rate()
269 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; in rkclk_pll_get_rate()
282 u32 con; in rockchip_mmc_get_clk() local
287 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
[all …]
H A Dclk_pll.c374 u32 con = 0, shift, mask; in rk3036_pll_get_rate() local
378 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
383 mode = (con & mask) >> shift; in rk3036_pll_get_rate()
392 con = readl(base + pll->con_offset); in rk3036_pll_get_rate()
393 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> in rk3036_pll_get_rate()
395 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> in rk3036_pll_get_rate()
397 con = readl(base + pll->con_offset + 0x4); in rk3036_pll_get_rate()
398 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> in rk3036_pll_get_rate()
400 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> in rk3036_pll_get_rate()
402 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >> in rk3036_pll_get_rate()
[all …]
/rk3399_rockchip-uboot/drivers/sound/
H A Dsamsung-i2s.c62 unsigned int con = readl(&i2s_reg->con); in i2s_txctrl() local
66 con |= CON_ACTIVE; in i2s_txctrl()
67 con &= ~CON_TXCH_PAUSE; in i2s_txctrl()
69 con |= CON_TXCH_PAUSE; in i2s_txctrl()
70 con &= ~CON_ACTIVE; in i2s_txctrl()
74 writel(con, &i2s_reg->con); in i2s_txctrl()
281 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { in i2s_transfer_tx_data()
334 writel(CON_RESET, &i2s_reg->con); in i2s_tx_init()
/rk3399_rockchip-uboot/drivers/i2c/
H A Drk_i2c.c89 debug("i2c_con: 0x%08x\n", readl(&regs->con)); in rk_i2c_show_regs()
211 static int rk_i2c_send_start_bit(struct rk_i2c *i2c, u32 con) in rk_i2c_send_start_bit() argument
220 writel(I2C_CON_EN | I2C_CON_START | i2c->cfg | con, &regs->con); in rk_i2c_send_start_bit()
237 writel(I2C_CON_EN | i2c->cfg | con, &regs->con); in rk_i2c_send_start_bit()
250 writel(I2C_CON_EN | i2c->cfg | I2C_CON_STOP, &regs->con); in rk_i2c_send_stop_bit()
275 writel(0, &i2c->regs->con); in rk_i2c_disable()
287 uint con = 0; in rk_i2c_read() local
298 writel(0, &regs->con); in rk_i2c_read()
312 con = I2C_CON_EN; in rk_i2c_read()
319 con = I2C_CON_EN | I2C_CON_LASTACK; in rk_i2c_read()
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