clk: rockchip: rk3288: support pclk_rkpwm get rate

Change-Id: I9c4016cdf1116586369c29eefcb9a1cb529c6ef9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: add clk_test setting

Change-Id: I3c3696d96e83cfad88ad417b322f65f079f1d702
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: Fix i2c clk rate calc

Change-Id: I083e2b8ceaa3eee7729174aa2e17b8a08cec9c05
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

clk: rockchip: rk3288: support get pll config by table

add some special pll configs for better clock jitter.

Change-Id: I93f8cab2a995fc584322070e25bbba6067c80dbb
Signed-off-by: Elaine Zhang <zhangq

clk: rockchip: rk3288: support get pll config by table

add some special pll configs for better clock jitter.

Change-Id: I93f8cab2a995fc584322070e25bbba6067c80dbb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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Merge branch 'next-dev' into thunder-boot

Change-Id: I35db1f0aa79575e972942b5c366f380fc8106343

clk: rockchip: rk3288: Reduce the hevc clock init frequency

Solve the video clock high frequency reset problem.

Change-Id: I2db4021d8c20d572bda045256360f4e9bed9f85c
Signed-off-by: Elaine Zhang <zha

clk: rockchip: rk3288: Reduce the hevc clock init frequency

Solve the video clock high frequency reset problem.

Change-Id: I2db4021d8c20d572bda045256360f4e9bed9f85c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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Merge branch 'next-dev' into thunder-boot

rockchip: rk3288: no need to check PLL setting.

Remove assert to make DEBUG work.

Change-Id: Idd41066f98c759b4fefe25c8715138c1c54df418
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

clk: rockchip: rk3288: fix up the assert error

Change-Id: I066a217b15108db21821c63bd7709fb430d34f45
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: support pclk_wdt get rate

Change-Id: I99f384344feb68ae5b91ade901df4019790ef8db
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: add clk_set_default

support aclk_vio\hclk_vio clk setting.

Change-Id: Ie826c770670598161f22208f504d8762b8597811
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: print arm enter and init rate

Change-Id: I5a6d564a973111841df6b53a4df64a54f728e116
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: support crypto clk setting

Change-Id: I066ec163d959b95d0928e07716e3370715aa9898
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: adjust gpll init_cfg

This patch adjust gpll init nr/no/nf/bw values.
keep them the same as kernel RK3066_PLL_RATE_NB(594000000, 2, 198, 4, 1)
for better clock jitter when hdmi

clk: rockchip: rk3288: adjust gpll init_cfg

This patch adjust gpll init nr/no/nf/bw values.
keep them the same as kernel RK3066_PLL_RATE_NB(594000000, 2, 198, 4, 1)
for better clock jitter when hdmi SI test.

Change-Id: I781205d860945214f3f0957882223b8846c00773
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

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clk: rockchip: rk3288: support aclk_vop freq setting

Change-Id: Ifb595f244608378bff1e6443dfc017418f28ce2a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: fix up the dclk_vop setting freq error

fix the commit b328c914c:
(clk: rockchip: rk3288: fix up the dclk_vop freq setting)

Change-Id: Ic4df8bcd4410dbc0484c1ea50d73e70aa64556b

clk: rockchip: rk3288: fix up the dclk_vop setting freq error

fix the commit b328c914c:
(clk: rockchip: rk3288: fix up the dclk_vop freq setting)

Change-Id: Ic4df8bcd4410dbc0484c1ea50d73e70aa64556bb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3288: fix up the dclk_vop freq setting

Change-Id: I960a02cba63076afbc845e5ccdfb9f85a553d38b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: support clk_tsadc setting freq

Change-Id: Ie5e91c95d6ff3caf618ff1a5e5e3b7dcf6723325
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: add PLL_LIMIT_FREQ

npll is for dclk, add PLL_LIMIT_FREQ for better jitter.

Change-Id: I6ac09e9bdbd1bef0eddb37835100be782b772d54
Signed-off-by: Elaine Zhang <zhangqing@rock-ch

clk: rockchip: rk3288: add PLL_LIMIT_FREQ

npll is for dclk, add PLL_LIMIT_FREQ for better jitter.

Change-Id: I6ac09e9bdbd1bef0eddb37835100be782b772d54
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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rockchip: clk: rk3288: convert to live dt

Use dev_read_addr_ptr to get cru base

Change-Id: Ia0c7e42beff1442055156d2125d35a58b5be8b13
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: clk: rk3288: do rkclk_init() when CPLL is in slow mode

The pre-loader(eg. miniloader) may not init the CPLL, we need to
do the rkclk_init() to init the clocks in U-Boot, or else we may
get

rockchip: clk: rk3288: do rkclk_init() when CPLL is in slow mode

The pre-loader(eg. miniloader) may not init the CPLL, we need to
do the rkclk_init() to init the clocks in U-Boot, or else we may
get wrong serial baurd rate in kernel.

Change-Id: I4a226e110638aa18d10df35e8d9507f6679a5678
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: Correct and standardize clock divisor range assertions

Some of the asserts for valid clock divisor ranges were off by one. This
patch corrects them and writes them all in a consistent

clk: rockchip: Correct and standardize clock divisor range assertions

Some of the asserts for valid clock divisor ranges were off by one. This
patch corrects them and writes them all in a consistent way.

Change-Id: Ia87974c8e27b7414cfe9210a916d114aa81f5ccb
Signed-off-by: Lin Huang <hl@rock-chips.com>

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rockchip: clk: guard set_parent implementations against OF_PLATDATA

The set_parent implementations do not make sense when OF_PLATDATA is
enabled. We guard these against OF_PLATDATA and don't popula

rockchip: clk: guard set_parent implementations against OF_PLATDATA

The set_parent implementations do not make sense when OF_PLATDATA is
enabled. We guard these against OF_PLATDATA and don't populate the
set_parent-op when this is the case.

Change-Id: I37c384bf6851666550b8b3902d79b9278cff5074
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>

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clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"

The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but wh

clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"

The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.

Change-Id: Ic1a41634aba674001beb0e7e5ca3f7f2fa008e51
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5

rockchip: clk: add device_bind_driver_to_node for reset driver

all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.

Change-Id: I03c2a798d211fb4181d5fc0fd6db8609c6db04d2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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